Hybrid buffers based coarse-grained power gated network on chip router microarchitecture

ABSTRACT

With the failure of Dennard’s Scaling, we cannot power on all the transistors of an circuit simultaneously for a given thermal design power. In this paper, we propose coarse-grained power gated hybrid buffer based Network on Chip router microarchitecture which a large amount of Network on Chip router power and area is consumed by the FIFO buffers. State of the art NoC router buffers is composed of SRAM, which is neither power efficient nor area efficient. We have proposed hybrid buffers based coarse-grained power gated Network on Chip router microarchitecture. As STT-MRAM (Spin Transfer Torque Magneto-resistive Random Access Memory) provides an improved solution having near zero leakage power and higher package density. Our proposed router microarchitecture improves 12.3% average packet latency as compared to state of the art power gated SRAM based router and 4.90% as compared to the fine-grained power gated hybrid buffer based router respectively for PARSEC benchmarks. We have achieved 65% and 21.34% total network energy saving for PARSEC benchmarks as compared with one without power gating and state of the art power gated SRAM based router respectively. Our hybrid router is 35.10% area efficient as compare to pure SRAM based power gated router at 32nm technology node.

KEYWORDS:

• Multi-core
• network on chip router
• STT-MRAM
• low power
• hybrid buffer

Acknowledgments

This work is partly supported by SMDPC2SD project, sponsored by “Ministry of Electronics & Information Technology, Government of India”.

Disclosure statement

No potential conflict of interest was reported by the authors.