A 5-MHz bandwidth 78.1-dB SNDR 2-2 MASH delta-sigma modulator

ABSTRACT

This paper presents a 4-bit, 2–2 multi-stage noise shaping (MASH) delta-sigma modulator (DSM) fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The DSM was designed using a cascade-of-integrators with a feedforward (CIFF) structure. The first integrator was designed to reduce the loading effect of the system’s front-end circuit using a switched-resistor integrator instead of the conventional switched-capacitor method. The CIFF structure requires an active adder, which is generally implemented with a high-bandwidth high-swing amplifier. In this paper, the active adder is eliminated and an adder-less integrator is implemented in the MASH DSM. The DSM prototype has an over-sampling ratio (OSR) of 16 and a 160 MHz sampling frequency. The prototype’s measured signal-to-noise ratio (SNR) is 82.4 dB and the signal-to-noise-plus-distortion ratio (SNDR) is 78.1 dB for a signal bandwidth of 5 MHz. The measured total power consumption is 26 mW at a 1.8 V supply voltage, and the chip core size is 0.67 mm². The energy required per conversion step is 0.4 pJ/conv.

KEYWORDS:

• ADC
• delta–sigma modulator
• hybrid switching integrator
• amplifiers
• communication system

Acknowledgments

This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Centre) support program (IITP-2019-2018-0-01421) supervised by the IITP (Institute of Information & communications Technology Planning & Evaluation). This research was supported by the MOTIE (Ministry of Trade, Industry & Energy) (project number 10080488) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device.

Disclosure statement

No potential conflict of interest was reported by the authors.