Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACT

Increasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

KEYWORDS:

• Reversible logic
• MGDI
• MGDI-FS
• Arithmetic unit
• quantum cost

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Swetha Siliveri

Siliveri Swetha received B.Tech degree in Electronic and communication engineering in 2008 from the JNTUH, Hyderabad and ME, degree in Embedded Systems and VLSI Design in 2012 from Osmania University, Hyderabad. She has 11 years of teaching experience. She is working as Sr.Assistant Professor in the Department of Electronics and Communication Engineering at CVR College of Engineering, Ibrahimpatnam, Hyd and Part-Time PhD Research Scholar in UCE, OU. Her research interest covers Digital Circuits, Low power VLSI Design, Computer Architecture.

N. Siva Sankara Reddy

Dr. Nuka Siva Sankara Reddy, received, M.Tech (Digital Systems & Computer Electronics) in 2000 and PhD degree in VLSI DESIGN from JNTUH Hyd in 2010. He is working as Associate Professor in Vasavi College of Engineering, Hyd. He has 30 years of teaching experience. His areas of research include Low Power VLSI Design, Digital Electronics, FPGA.