Novel dual power hybrid write operation structure for STT-MRAM

ABSTRACT

Due to the inherent physical characteristics and the influence of process variation, the write operation in the 1T–1 R STT-MRAM bit-cell shows critical issues of asymmetric and stochastic. In the paper, a low power write circuit with a novel dual power hybrid (NDPH) structure is presented to address the issues. The designed write circuit includes the NDPH structure, write verification circuit and write self-termination circuit, etc. It can be used to detect the write operation status in real-time. Based on the detection, the status of the write driver can be adjusted on time. The proposed write circuit in the paper can save about 50% of the power consumption. The write voltage can be reduced to 0.68 V. The proposed circuit shows a potential application for low-power writing operation in STT-MRAM.

KEYWORDS:

• STT-MRAM
• write operation completion detection circuit
• write self-termination circuit

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work is supported by Open Project Funding of State Key Laboratory of Processor Chip (CLQ202303) and National Science Foundation of China (61774078).