An energy-efficient design of ternary SRAM using GNRFETs

ABSTRACT

The primary requirement of internet-of-things (IoT) applications is to have an energy-efficient design that extends the battery life for long-term operation. To achieve energy efficiency, one can employ multiple-valued logic (MVL) instead of binary logic and utilise graphene nanoribbon field-effect transistors (GNRFETs) as variable-threshold voltage (V_th) capable devices. The implementation of an MVL system enhances data transferability and reduces the number of interconnections, resulting in improved energy consumption compared to a binary system. In such systems, static random access memory (SRAM), which serves as a crucial component of very large-scale integrated (VLSI) chips, dominates energy consumption. This research paper introduces an energy-efficient ternary SRAM using GNRFETs. We propose a standard ternary inverter based on GNRFET devices, which serves as the fundamental building block of a storage cell. Simulation results conducted on a 32-nm GNRFET with a 0.9 V supply voltage demonstrate that the proposed design achieves energy consumption improvements ranging from 46.39% to 98.16% compared to the most recent ternary SRAMs. Furthermore, the SRAM cell is evaluated under various processes and environmental parameter variations.

KEYWORDS:

• Static random access memory (SRAM)
• ternary logic
• standard ternary inverter (STI)
• graphene nanoribbon field-effect transistor (GNRFET)

Acknowledgements

This research is funded by the Babol Noshirvani University of Technology, under research grant No. P/M/1123.

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Funding

This work was supported by the Babol Noshirvani University of Technology [P/M/1123].