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International Journal of Electronics Volume 79, 1995 - Issue 5
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Circuit techniques and analysis

Evaluation of metastability transfer models: an application to an N-bistable CMOS synchronizer

M. J. BELLIDO Departamento de Tecnología Electrónica, Universidad de Sevilla, Sevilla, 41012, Spain; Departamento de Diseño de Circuitos Analógicos, Centro Nacional de Microelectronica-CSIC, Edificio CICA, C/ Tarna s/n, Sevilla, 41012, SpainView further author information
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A. J. ACOSTA Departamento de Electrónica y Electromagnetismo, Universidad de Sevilla, Spain; Departamento de Diseño de Circuitos Analógicos, Centro Nacional de Microelectronica-CSIC, Edificio CICA, C/ Tarna s/n, Sevilla, 41012, Spain
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J. LUQUE Departamento de Tecnología Electrónica, Universidad de Sevilla, Sevilla, 41012, Spain
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A. BARRIGA Departamento de Electrónica y Electromagnetismo, Universidad de Sevilla, Spain; Departamento de Diseño de Circuitos Analógicos, Centro Nacional de Microelectronica-CSIC, Edificio CICA, C/ Tarna s/n, Sevilla, 41012, Spain
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M. VALENCIA Departamento de Tecnología Electrónica, Universidad de Sevilla, Sevilla, 41012, Spain; Departamento de Diseño de Circuitos Analógicos, Centro Nacional de Microelectronica-CSIC, Edificio CICA, C/ Tarna s/n, Sevilla, 41012, Spain
Pages 585-593 | Received 13 Mar 1995, Accepted 02 Jun 1995, Published online: 19 Apr 2007
 
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Abstract

This paper deals with the metastability transfer in CMOS bistables, its modelling, and its application to the evaluation of the mean time between failures (MTBF) of synchronizers consisting of N bistables in cascade. Simulation results show that a widely used classic model is not realistic.

Notes

Tel: +(34) 5 423 9923; Fax: +(34) 5 4624506

Additional information

Notes on contributors

M. J. BELLIDO

[email protected].

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