Detecting over Rejection in Testing of Integrated Circuits

Abstract

In parallel testing of integrated circuits (IC's), IC's which are conforming in terms of electrical functionality are sometimes incorrectly rejected. This is commonly known as over rejection. Over rejection is due to faulty sockets or failed components of the test hardware system associated with the socket locations. In this paper we propose a two-stage procedure for monitoring socket locations causing an over rejection: in stage one, a binomial test of proportions is used to identify socket locations which are causing an over rejection; in stage two, a cumulative sum scheme is used to monitor the socket locations to detect possible failures of components of the test hardware system. Detection of faulty sockets or failed components results in a reduction of rejected conforming IC's. A simple method is provided for the design of such a procedure. Formulas are also provided which allow the performance of the scheme to be evaluated. An application of the procedure in parallel testing of IC's is performed. A follow up study is conducted to determine practical problems with the procedure and to find solutions.

• Bernoulli Distribution
• Binomial Distribution
• Cumulative Sum Control Charts
• Statistical Process Control

Additional information

Notes on contributors

T. C. Chang

Dr. Chang is a Process Control Specialist.

F. F. Gan

Dr. Gan is an Associate Professor in the Department of Statistics and Applied Probability. He is Member of ASQ. His email address is [email protected].