Implementation Aspects of Logic Functions using Single Electron Threshold Logic Gates and Hybrid SET-MOS Circuits

ABSTRACT

Single electron technology is an attractive technology for future low-power VLSI/ULSI systems. Single electronics implies the possibility to control the movement and position of a single electron or a small amount of electrons. In this work, design, implementation, and analysis of logic functions are presented using single electron threshold logic gate (TLG) and hybrid SET-MOS circuits. The logic operation of the designed circuit is tested using Monte Carlo-based simulation tool SIMON for the single electron threshold logic circuit. For the hybrid SET-MOS-based implementation, the logic operation of the circuit is verified in Tanner environment. A compact analytical model with 11 island states for SET devices and BSIM4.6.1 model for MOS is used. The influence of thermal fluctuation on the stability of the threshold logic-based circuit, caused by increase in system temperature, has been thoroughly investigated. The effect of island states on the performance of the hybrid SET-MOS circuit is analysed. Finally, the performances of both the design approaches have been analysed and compared in terms of circuit elements, voltage levels, power consumption, and delay.

KEYWORDS:

• delay
• hybrid SET-MOS
• Island States
• Single electron transistor (SET)
• programmable logic array (PLA)
• power dissipation
• SIMON
• stability plot
• threshold logic gate (TLG)

Acknowledgments

Subir Kumar Sarkar thankfully acknowledges the financial support obtained from UGC UPE-Phase II project, Jadavpur University, India.

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

UGC UPE-Phase II project (MIAJRF-10), India.

Notes on contributors

Amit Jain

Amit Jain obtained B.Tech degree in electronics and communication engineering from MCKV Institute of Engineering, West Bengal, India, in 2009. He obtained M. Tech degree in Microelectronics and VLSI Design from NIT Silchar, Assam, India, in 2011. Currently, he is working towards his PhD degree. His current research interest includes modelling and simulation of nano-electronics devices, single electron transistors, design and analysis of hybrid SET-MOS circuits.

E-mail: [email protected]

Arpita Ghosh

Arpita Ghosh obtained B.Tech degree in electronics and communication engineering from Asansol engineering college, West Bengal, India, in 2008. She obtained M. Tech degree in embedded system from Haldia Institute of Technology, West Bengal, India, in 2010. Currently, she is working as an assistant professor in RCC Institute of Information Technology, Kolkata, India. Her current research interest includes modelling and simulation of single electron transistor, design and simulation of hybrid SET-MOS circuits.

E-mail: [email protected]

N. Basanta Singh

N. Basanta Singh received his B.Tech degree in electronics and communication engineering from Kerala University, Kerala, India, in 1992, ME degree in electronics and communication engineering from Thapar Institute of Engineering and Technology, Patiala, India, in 2000 and the PhD degree in electronics and communication engineering from NIT, Durgapur, in 2013. He is currently associate professor and head, Department of Electronics and Communication Engineering, Manipur Institute of Technology, Manipur University, Manipur, India. He has published more than 38 technical research papers in archival journals and peer-reviewed conferences. His current research interests include modelling and simulation of nano-devices, design and modelling of single electron devices.

E-mail: [email protected]

Subir Kumar Sarkar

Subir Kumar Sarkar received his B. Tech, M. Tech, and PhD degrees from the Institute of Radio Physics and Electronics, University of Calcutta, India, and post-doctoral fellow from the Department of Electrical and Computer Engineering, Virginia Commonwealth University, USA. He is a professor and former head of the Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India. He has published five engineering text books and a few are in the pipeline. He has published more than 450 technical research papers in archival journals and peer-reviewed conferences. His most recent research focuses are in the areas of nanodevices and low-power VLSI circuits. He is a senior member of IEEE, life fellow of IE (India), and life fellow of IETE.

E-mail: [email protected]