Reversible Comparator Design Using Quantum Dot-Cellular Automata

ABSTRACT

Quantum dot-cellular automata (QCA) emerge as a research area to design nanometre scale logic circuit. In digital logic design, a comparator is the fundamental building block that performs the comparison of two numbers. This paper deals with the design of reversible building block for 1-bit comparator and its implementation in QCA. An improved QCA layout of Feynman gate is also achieved. The QCA Feynman gate is denser and has low delay than the existing circuit. The proposed reversible comparator has quantum cost 9, whereas the QCA reversible comparator has the quantum cost 0.927. The quantum cost based comparison of the proposed QCA reversible comparator with conventional reversible comparator shows the cost effective circuit design in QCA. The simulation result matched the truth table of comparator which approves the functional capability of the proposed QCA layout of comparator. All the proposed layouts dissipate very low power.

KEYWORDS:

• Feynman gate
• majority gate
• QCA
• reversible comparator
• TR gate

Acknowledgement

The authors are grateful to The University Grants Commission, India, for providing with the grant for accomplishment of the project under the UGC Major Project File No. 41-631/2012(SR).

Disclosure statement

No potential conflict of interest was reported by the authors.

Additional information

Funding

The University Grants Commission, India: UGC Major Project [grant number 41-631/2012(SR)].

Notes on contributors

Jadav Chandra Das

Jadav Chandra Das received his MTech degree in Multimedia and Software Systems from WBUT, West Bengal, India, in 2011. Presently he is an assistant professor in the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology under WBUT, Kolkata, India. His research interest includes cryptography, QCA-based image processing, and reversible logic circuit design.

E-mail: [email protected]

Debashis De

Debashis De received his MTech degree in Radio Physics and Electronics in 2002. He obtained his PhD degree (Engineering) from Jadavpur University in 2005. Presently he is an associate professor in the Department of Computer Science and Engineering, WBUT, India, and Adjunct Research Fellow in University of Western Australia, Australia. He was awarded the prestigious Boyscast Fellowship by the Department of Science and Technology, Govt. of India, to work at Herriot-Watt University, Scotland, UK. He received Young Scientist award both in 2005 at New Delhi and in 2011 at Istanbul by International Union of Radio Science, H.Q., Belgium. His research interest includes location management and power consumption control in mobile network and low power nano device design for mobile application and disaster management.

E-mail: [email protected]