A Novel Time-to-Digital Converter Based on Low-Jitter Phase-Locked Loop

ABSTRACT

This paper presents a novel multi-levels time-to-digital converter (TDC) suitable for array architecture for the photon time-of-flight (TOF) measurement. A simple method was applied to solve the initial phase time mismatch caused by random occurrence of the TOF start signal. A low-jitter phase-locked loop (PLL) is adopted to provide excellent clocks to the TDC. The proposed PLL–TDC has a good differential nonlinearity (DNL) (±0.4 LSB) and integral nonlinearity (INL) (±0.5 LSB) due to the low-jitter clock and elimination of initial phase time mismatch. The circuit of the low-jitter PLL was implemented in TSMC 0.35 µm standard complementary metal oxide semiconductor (CMOS) process with 3.3 V supply voltage. The measured result of the low-jitter PLL and the simulated result of the TDC show the proposed 14-bit TDC can realize 1.0 ns time resolution and 16 µs maximum range with 125 MHz centre frequency. Under this given frequency, the time interval error (TIE) jitter is 7.8 ps_(rms).

KEYWORDS:

• Initial phase time mismatch
• Low-jitter phase-locked loop
• Time-of-flight (TOF) Measurement
• Time-to-digital converter (TDC)

DISCLOSURE STATEMENT

No potential conflict of interest by reported by the authors.

Additional information

Funding

This work was supported by the National Key Research and Development Program of China [grant number 2016YFB0400904].

Notes on contributors

Jin Wu

Jin Wu was born in Jiangsu Province, China in 1965. He received B.S., M.S. and Ph.D. degrees in Electrical Engineering from Southeast University, China, in 1988, 1991, 1997, respectively. His recent research interests focus on low-power high-speed configurable analog integrated circuit design, time-to-digital converter and readout integrated circuit design for single-photon detection 3D imaging applications. He is currently with School of Integrated Circuit in Wuxi Branch of Southeast University, Wuxi, China.

E-mail: [email protected]

Chao Wang

Chao Wang was born in Hubei Province, China in 1991. He received the B.S. degree from Hubei University, China in 2014. Now he is pursuing the M.S. degree in Institute of Integrated Circuit at Southeast University, Nanjing, China. His research interests include digital clock circuit, time-to-digital converter, and readout integrated circuit for single photon detection 3D imaging application.

E-mail: [email protected]

Shu-fang Shi

Shufang Shi received the B.S. degree from Hangzhou Dianzi University, Hangzhou, China in 2015. Now he is pursuing the M.S. degree in Institute of Integrated Circuit at Southeast University, Nanjing, China. He is engaged in the research on mixed digital and analog integrated circuits.

E-mail: [email protected]

Xiang-rong Yu

Xiangrong Yu received the B.Sc. Degree from Shandong University, Jinan, China in 2015. Now he is working toward M.Sc. degree in integrated circuits in Southeast University, Nanjing, China.

E-mail: [email protected]

Li-xia Zheng

Lixia Zheng received the M.S. degree from Nanjing University of Science and Technology, Nanjing, China in 2004. Now she is pursuing the Ph.D. degree in IC design at Southeast University, Nanjing, China. Her research interests include mixed-signal integrated circuit design, readout circuit of SPAD.

E-mail: [email protected]

Wei-feng Sun

Weifeng Sun, IEEE senior member, received the B.S., M.S. and Ph.D. degrees in electronic engineering from Southeast University, in 2000, 2003 and 2007, respectively. His research interests mainly include readout integrated circuit design for single-photon detection 3D imaging applications, new power device design, power IC, power device model, power IC and RF device design.

E-mail: [email protected]