A Novel Design of a Multiplier Using Reversible Ternary Gates

ABSTRACT

Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.

KEYWORDS:

• Quantum computer
• Reversible ternary Logic
• Full-adder
• Multiplier

Additional information

Notes on contributors

Mohammad Mehdi Panahi

Mohammad Mehdi Panahi received his MSc degree from Science and Research Branch, Islamic Azad University, Tehran, Iran, in computer architecture engineering. He is currently a PhD candidate in computer architecture at Science and Research Branch, Islamic Azad University. He is working on reversible circuit design. Email: [email protected]

Omid Hashemipour

Omid Hashemipour (BS 1985, MS 1987, PhD 1991) in electrical engineering, all received from University of Arkansas at Fayetteville USA. From 1991, he is with the Electrical Engineering Faculty at Shahid Beheshti University, GC, Tehran, Iran as an associate professor. His research interests include mix mode and low-power, low-voltage, and current mode analog integrated circuits.

Keivan Navi

Keivan Navi received MSc degree in electronics engineering from Sharif University of Technology, Tehran, Iran in 1990. He also received the PhD degree in computer architecture from Paris XI University, Paris, France, in 1995. He is currently a full professor in Faculty of Electrical and Computer Engineering of Shahid Beheshti University. His research interests include nano electronics with emphasis on CNFET, QCA and SET, computer arithmetic, interconnection network design and quantum computing and cryptography. Email: [email protected]