An Area Efficient Sub-threshold Voltage Level Shifter using a Modified Wilson Current Mirror for Low Power Applications

Abstract

In the present communication, a new technique has been introduced for implementing low-power area efficient sub-threshold voltage level shifter (LS) circuit. The proposed LS circuit consists of only nine transistors and can operate up to 100 MHz of input frequency successfully. The proposed LS is made of single threshold voltage transistors which show least complexity in fabrication and better performance in terms of delay analysis and power consumption compared to other available designs. CAD tool-based simulation at TSMC 180 nm technology and comparison between the proposed design and other available designs show that the proposed design performs better than other state-of-the-art designs for a similar range of voltage conversion with the most area efficiency.

KEYWORDS:

• Current mirror
• CAD simulation
• Level shifter (LS)
• Low power
• Sub-threshold operation
• Typical transistor (TT)

Additional information

Notes on contributors

Biswarup Mukherjee

Biswarup Mukherjee received UG & PG degrees in electronics and communication engineering in 2008 and 2010, respectively. He is currently working as an assistant professor of electronics and communication engineering at Neotia Institute of Technology, Management and Science. He is pursuing his research from the University of Calcutta and his research interest is in the domain of low-power VLSI design. His major contribution includes CCGDI-based low-power VLSI circuit design. Corresponding author. Email: [email protected]

Aniruddha Ghosal

Aniruddha Ghosal received his BSc and BTech from the University of Calcutta, India in 1976 and 1979, respectively. He obtained his MTech with specialization in semiconductor electronics in 1981. He was awarded PhD from the Calcutta University in 1989 for the dissertation on electron transport in bulk and quantum well structure of polar semiconductor. He was awarded Commonwealth Scholarship in 1989 for research in Semiconductor Superlattice structures in the University of Essex in U.K. He joined as an assistant professor in Radio Physics and Electronics, the Calcutta University, India in 1989 and is still working there as a professor. His research interest is electron transport in semiconductor low dimensional system, nanostructures and VLSI. He has more than 50 publications in journals of International repute. Email: [email protected]