Delay and Energy Efficient Modular Hybrid Adder for Signal Processor Architectures

Abstract

In this modern era, high-performance energy efficient devices/systems are the basic requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the frequently used elements in majority of the signal processing architectures. In an MAC unit adders are the basic components. To this end, delay and energy efficient modular hybrid adders for various bit widths are presented. The adder structures are obtained by combining the concatenation and the incrementation schemes to a hybrid structure consisting of modified forms of ripple, carry look ahead, and carry skip adder sections so as to improve delay and energy efficiency. Two versions of hybrid adder architectures are proposed. For n-bit addition, the first adder architecture consists of m numbers of k-bit modified hybrid carry look ahead adder modules, k-bit final sum logic (FSL) stages and output fast carry logic (OFCL) stages. The second adder structure is obtained from the first adder structure by replacing FSL with modified FSL. The speed of addition is improved by the quick and parallel generation of end carry of concatenated adder stages by the modified look ahead carry generation blocks and by the transmission of carries through the modified carry skip action performed by the OFCL blocks. Cadence software with gpdk standard libraries of 45, 90 and 180 nm technology nodes are used for the design and implementation. The values of delay, PDP, and ADP obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency.

KEYWORDS:

• Concatenation
• Critical path delay
• Hybrid adder
• Incrementation
• Power
• Processor
• RTL compiler

Additional information

Notes on contributors

P. Pramod

P Pramod received his Master of Engineering degree in VLSI design from Anna University, Chennai. He is an assistant professor in the Department of Electronics and Communication Engineering, Lal Bahadur Shastri College of Engineering, Kasaragod, Kerala, India. He is currently a PhD candidate in Division of Electronics, School of Engineering, Cochin University of Science and Technology (CUSAT), Kerala, India. His current interest includes digital system design, low-power techniques, VLSI design & testing, and VLSI signal processing. He is a life member of Indian Society of Technical Education. He has completed the Executive Program for Young Professionals from IIM Calcutta and Master of Business Administration from ICFAI University.

T. K. Shahana

T K Shahana is a professor at Cochin University of Science and Technology (CUSAT), Kerala, India. She received her PhD in VLSI design from Cochin University of Science and Technology in 2009, MTech in digital electronics from CUSAT in 1999 and BTech in electronics and communication engineering from Mahatma Gandhi University in 1997. Her research interests include VLSI implementation of digital systems, digital filters, multi-standard wireless transceivers, RNS-based arithmetic circuits, low-power design, etc. Email: [email protected]