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Review Articles

Delay and Energy Efficient Modular Hybrid Adder for Signal Processor Architectures

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References

  • P. K. Meher, and S. Y. Park, “Critical-path analysis and low-complexity implementation of the LMS adaptive algorithm,” IEEE Trans. Circuits Syst.-I: Reg. Pap., Vol. 61, no. 3, pp. 778–88, 2014. doi: 10.1109/TCSI.2013.2284173
  • P. K. Meher, and S. Y. Park, “Area-delay-power efficient fixed-point LMS adaptive filter with low adaptation-delay,” IEEE Trans. VLSI Syst., Vol. 22, no. 2, pp. 362–71, 2014. doi: 10.1109/TVLSI.2013.2239321
  • A. P. Chandrakasan, N. Verma, and D. C. Daly, “Ultralow-power electronics for biomedical applications,” Annu. Rev. Biomed. Eng., Vol. 10, pp. 247–74, 2008. doi: 10.1146/annurev.bioeng.10.061807.160547
  • B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs. New York, USA: Oxford University Press.
  • M. D. Ercegovac, and T. Lang. Digital Arithmetic. San Mateo, CA: Mogan Kaufmann, 2004.
  • J. M. Rabaey, A. Chandrakasa, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, 2003.
  • S. Ghosh, D. Mohapatra, G. Karakonstantis, and K. Roy, “Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking,” IEEE Trans. Very Large Scale Integr. Syst., Vol. 18, no. 9, pp. 1301–9, Sep. 2010. doi: 10.1109/TVLSI.2009.2022531
  • R. W. Doran, “Variants of an improved carry look-ahead adder,” IEEE Trans. Comp., Vol. 37, no. 9, pp. 1110–3, 1988. doi: 10.1109/12.2261
  • M. Alioto, and G. Palumbo, “A simple strategy for optimized design of one-level carry-skip adders,” IEEE Trans. Circuits Syst. I, Fundam.Theory Appl., Vol. 50, no. 1, pp. 141–8, Jan. 2003. doi: 10.1109/TCSI.2002.807517
  • R. P. Brent, and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. Comp., Vol. C-31, no. 3, pp. 260–4, 1982. doi: 10.1109/TC.1982.1675982
  • T. Han, and D. A. Carlson. “Fast area-efficient VLSI adders,” in Proceedings of the 8th IEEE Symposium on Computer Arithmetic, Como, Italy, May 1987, pp. 49–56.
  • S. K. Mathew. “A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core,” in Symposium on VLSI Circuits Digest of Technical Papers. Hillsboro, USA: Circuits Research, Intel Labs, Intel Corporation, 2002, pp. 126–7.
  • H. Q. Dao, B. R. Zeydel, and V. G. Oklobdzija, “Energy optimization of pipelined digital systems using circuit sizing and supply scaling,” IEEE Trans. VLSI Syst., Vol. 14, no. 2, pp. 122–34, 2006. doi: 10.1109/TVLSI.2005.863760
  • Y. He, and C.-H. Chang, “A power-delay efficient hybrid carrylookahead/carry-select based redundant binary to two’s complement converter,” IEEE Trans. Circuits Syst.-I Reg. Pap., Vol. 55, no. 1, pp. 336–46, Feb. 2008. doi: 10.1109/TCSI.2007.913610
  • K. Chirca, M. Schulte, J. Glossner, H. Wang, B. Mamidi, P. Balzola, and S. Vassiliadis. “A static low-power, high-performance 32-bit carryskip adder,” in Proceedings of Euromicro Symposium on Digital System Design (DSD), Rennes, France, Aug. 31–Sep. 3, 2004, pp. 615–9.
  • Y. Chen, H. Li, C. K. Koh, G. Sun, J. Li, Y. Xie, and K. Roy, “Variable-latency adder (VL-adder) designs for low power and NBTI tolerance,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 18, no. 11, pp. 1621–4, Nov. 2010. doi: 10.1109/TVLSI.2009.2026280
  • S. Jia, F. Liu, J. Gao, L. Liu, X. Wang, T. Zhang, Z. Chen, and L. Ji. “Static CMOS implementation of logarithmic skip adder,”in Proceedings of IEEE Conference on Electron Devices Solid-State Circuits, Hong Kong, China, Dec. 2003, pp. 509–12.
  • O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron. Comput., Vol. EC-11, no. 3, pp. 340–6, 1962. doi: 10.1109/IRETELC.1962.5407919
  • B. K. Mohanty, and S. Kumar, “Patel area–delay–power efficient carry-select adder,” IEEE Trans. Circuits Syst.-II: Exp. Briefs, Vol. 61, no. 6, pp. 418–22, 2014. doi: 10.1109/TCSII.2014.2319695
  • B. Ramkumar, and H. M. Kittur, “Low-power and area-efficient carry-select adder,” IEEE Trans. Very Large Scale Integ. Syst., Vol. 20, no. 2, pp. 371–5, 2012. doi: 10.1109/TVLSI.2010.2101621
  • T. Y. Chang, and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett., Vol. 34, no. 22, pp. 2101–3, 1998. doi: 10.1049/el:19981706
  • Y. Kim, and L. S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., Vol. 37, no. 10, pp. 614–5, 2001. doi: 10.1049/el:20010430
  • M. Bahadori, M. Kamal, and A. Afzali-Kusha, “High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels,” IEEE Trans. Very Large Scale Integ. Syst., Vol. 24, no. 2, pp. 421–433, Feb. 2016. doi: 10.1109/TVLSI.2015.2405133
  • S. Thakral, D. Goswami, R. Sharma, C. K. Prasanna, A. Mahesh, and A. M. Joshi. “Design and implementation of a high speed digital FIR filter using unfolding”, in Proceedings of 7th IEEE Power India International Conference, Bikaner, India, 2016.
  • Cadence 45 nm, 90 nm and 180 nm gpdk standard cell libraries. Available: https://support.cadence.com/.

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