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Abstract
With the change in commuting paradigms, the demands in industries have changed accordingly. Consequently, efficient design models and related technologies have evolved as prime driving factors to this cause. In such a scenario, reversible logic design has come out as a prominent future technology which not only provides faster computing platform but also promises energy efficient designs. But it is also very evident that not only the efficient designs play a pivotal role in reliable design models but incorporation of proper testing mechanisms is very important. Further to contribute to this cause, here, in this work we introduce an efficient test vector generation method to detect all type of missing gate faults in reversible circuits. In our proposed scheme, we have explored the Boolean difference property of logic functions for designing a Boolean generator from which fault specific test vectors are computed for different fault models. The test vector generation method is composed of two phases. In first phase, a Boolean generator produces fault specific test vectors and in the second phase, we employ a repeated factoring technique over the generated test set to reduce the test size so that the testing process can be faster. We have tested our developed technique over a large spectrum of benchmarks and an improvement over existing testing works has been registered. We have achieved 71% improvements over test vector count in SMGF, 58% for MMGF and 78% for PMGF.
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Notes on contributors
Bappaditya Mondal
Bappaditya Mondal has obtained his BE degree in information technology from MCKV Institute of Engineering, affiliated to Vidyasagar University in 2004 and ME in information technology from West Bengal University of Technology (in house) in 2007. Having 8 years of teaching experience, starting with Bankura Unnayani Institute of Technology, Bankura in 2007, he has also served as assistant professor in Neotia Institute of Technology, Management and Science (formerly, ITME) in the Department of Computer Science and Engineering. He registered for his PhD in October 2015 in Indian Institute of Engineering Science and Technology, Shibpur under guidance of Dr Hafizur Rahaman, department of Information Technology, Indian Institute of Engineering Science and Technology, Shibpur. His area of research is testing of reversible quantum circuit. He is author of six international conference papers. Email: [email protected]
Chandan Bandyopadhyay
Chandan Bandyopadhyay has obtained his ME degree in information technology from Indian Institute of Engineering Science and Technology (IIEST) Shibpur in 2013 and presently serving as CSIR-Senior research fellow in Dept of Information Technology in Indian Institute of Engineering Science and Technology Shibpur. He is author of more than 20 international conferences and journals. He also has served as reviewer in several international journals. His interest of research is mainly in reversible logic synthesis, testing, quantum and in fault-tolerant circuit design. He is recipient of several awards.
Dipak Kumar Kole
Dipak Kumar Kole currently serving as head of Dept of Jalpaiguri Government Engineering College. He is deeply involved in teaching and has 17 years of teaching experience. Beside that he has obtained his PhD degree from Bengal Engineering and Science University, Shibpur after completion of his master and bachelor degree in computer science and engineering from University of Calcutta. His research interest is in the field of reversible circuit, digital water marking and social network analysis. He has published 8 international journals and 36 international conference papers. Email: [email protected]
Debesh Kumar Das
Debesh Kumar Das, born in 1960 has done his PhD in 1997 from Jadavpur University after completion of master and bachelor degrees, respectively in 1984 and 1982 in electronics & tele-communication engineering from the same University. Having 20 years of teaching experience, starting with Birla Institute of Technology, Mesra in 1986 and further as lecturer / reader in Calcutta University and Jadavpur University and subsequently as professor in the Department of Computer Science and Engineering at Jadavpur University. Besides teaching, he was very much involved in research with special interest in VLSI design, VLSI testing, logic synthesis, etc. and is having 23 years experience in this particular field. He did post-doctoral research work in Nara Institute of Science and Technology, Japan and University of Potsdam, Germany. He was a visiting professor of Asian Institute of Technology, Bangkok. He visited different countries like USA, Italy, China, Canada, Denmark and many more for research studies and presentations. He published more than 100 papers in international journals and proceedings of reputed international conferences. Eight students were awarded PhD under his guidance. Email: [email protected]
Hafizur Rahaman
Hafizur Rahaman (SM 2010) received his PhD degree in computer science and engineering from the Jadavpur University, Calcutta, India in 2003. Dr Rahaman is full professor of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. Dr Rahaman visited as post-doctoral research fellow under EPSARC Grant at the department of Computer Science, Bristol University, UK during 2006–2007. During 2008–2009, Dr Rahaman received Royal Society International Fellowship award to carry out one year advanced research in the Design and Verification Division of Computer Science Department, University of Bristol, United Kingdom. Recently he received DST-DAAD research fellowship under Indo-German (DST-DAAD) Bilateral Cooperation in 2013. His research interests include design and testing of Integrated Circuits and nano-biochips, emerging nanotechnologies including reversible computing. He has published more than 300 research articles in archival Journals and refereed conference proceedings. He leads the VLSI design and test group at IIEST, Shibpur, India. Dr Rahaman is a Member of the VLSI Society of India (VSI), the IEEE, the IEEE Computer Society, and ACM Sigda. He is regular reviewer of IEEE TCAD, IEEE TVLSI, IEEE TC, and ACM TODAEs. He served on the conference committees of VLSI Design, VDAT, ATS, ISED, ISPD etc. Email: [email protected]