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ABSTRACT
Power consumption issues in VLSI circuits resulted in the emergence of promising technologies – like reversible computing. The introduction of such computing paradigm has turned out to be beneficial for the application of low power CMOS design, communications and in the emerging area of quantum computing. With these benefits, physical realization of reversible circuits has received significant attention in the semiconductor industry. Additionally, to make a robust implementation of this technology, testing has been considered an essential component and several works on this filed are being reported on a daily basis. Although, many works on the efficient detection of gate faults exist but our main focus is not only to detect the faults in the circuit but also to localize the fault with 100% accuracy. Considering this aspect, in this article we propose a fault detection and localization scheme for the existing missing gate fault models in reversible circuits. In our approach, initially test vectors (T) are computed and then an algorithm executes to generate a unique test set (U). Once the test set (U) is generated, it is applied to detect any type of faults if exist in the circuit. Our approach has been successfully tested for all types of missing gate faults – SMGF, PMGF and MMGF. In way to verify the functional correctness of our scheme, we also have executed the testing policy over a wide spectrum of benchmarks and experimental findings are cross checked. The obtained results have been compared with peer-reviewed works and improvements are reported.
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Notes on contributors
Bappaditya Mondal
Bappaditya Mondal has obtained his BE degree in information technology from M C K V Institute of Engineering, affiliated to Vidyasagar University in 2004 and ME in information technology from West Bengal University of Technology (in house) in 2007. Having 8 years of teaching experience, starting with Bankura Unnayani Institute of Technology, Bankura in 2007, he also served as assistant professor in Neotia Institute of Technology, Management and Science (formerly, ITME) in the Department of Computer Science and Engineering. He registered for his PhD in October 2015 in Indian Institute of Engineering Science and Technology, Shibpur. His area of research is testing of reversible quantum Circuit. He is an author of six international conference papers. E-mail: [email protected]
Chandan Bandyopadhyay
Chandan Bandyopadhyay obtained his ME degree from Indian Institute of Engineering Science and Technology (IIEST) Shibpur in 2013 and presently serving as CSIR-senior research fellow in Indian Institute of Engineering Science and Technology, Shibpur. He is author of more than 30 international conferences, journals and book chapters. He also has served as reviewer in several peer-reviewed international journals (SCI indexed) and conferences. He is recipient of several awards. His interest of research is mainly in reversible logic synthesis, testing, quantum and in fault-tolerant circuit design. Corresponding author. Email: [email protected]
Anirban Bhattacharjee
Anirban Bhattacharjee received BTech degree in information technology from B P Poddar Institute of Management and Technology, Kolkata, India in 2012 and subsequently the MTech degree in the same Department from Indian Institute of Engineering Science and Technology (IIEST), Howrah, India in 2016. He has worked as software developer in Cognizant Technology Solutions from 2012 to 2014 and served as assistant professor in Techno India University from 2016 to 2017. Currently, he is pursuing PhD in Indian Institute of Engineering Science and Technology (IIEST) Shibpur. Authored more than 10 peer-reviewed research papers and book chapters. His areas of interest include reversible logic synthesis, quantum circuit design, fault-testing and logic optimization. E-mail: [email protected]
Debashri Roy
Debashri Roy received her MS degree in computer science at University of Central Florida, where she is currently a PhD candidate. Her research interests are radio frequency machine learning systems (RFMLs), generative adversarial nets, real-time video transmission, vehicular networks, heterogeneous networks, modeling and simulation, dynamic spectrum access. E-mail: [email protected]
Shalini Parekh
Shalini Parekh obtained her BTech degree in computer science and engineering from West Bengal University of Technology in 2013, and MTech degree from Bengal Engineering and Science University in 2016. She worked in different industrial projects in collaboration with IIT-KGP while pursuing her masters. Her master's thesis was on “improved synthesis approach for ESOP based reversible circuit”. She also has experience working in multinational organizations, in IBM India Pvt Ltd for client Abbott Laboratories in Chicago (2016–2017). In mid-2017, she moved to Belgium and started working as a technical consultant (Embedded Software Engineer). She continued working as a consultant when she got the opportunity to pursue her PhD at ID Lab (IMEC-UGent) in Belgium as a Marie-Curie Research Fellow. She started her PhD in 2018 and is currently working on H2020 project - TAPAS (Training Network on Automatic Processing of Pathological Speech), where she is working in the field of machine learning and evidence-based speech therapy. Her research interests are in the field of quantum, synthesis of reversible circuits, algorithms, machine learning and speech processing. E-mail: [email protected]
Hafizur Rahaman
Hafizur Rahaman received his PhD degree in computer science and engineering from the Jadavpur University, Calcutta, India in 2003. Dr Rahaman is professor of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. Dr Rahaman visited as Post-doctoral research fellow under EPSARC Grant at the Department of Computer Science, Bristol University, UK during 2006–2007. During 2008–2009, Dr Rahaman received Royal Society International Fellowship award to carry out one-year advanced research in the Design and Verification Division of Computer Science Department, University of Bristol, United Kingdom. Recently, he received DST-DAAD research fellowship under Indo-German (DSTDAAD) Bilateral Cooperation in 2013. His research interests include design and testing of integrated circuits and nanobiochips, emerging nanotechnologies including reversible computing. He has published over 400 research articles. He leads the VLSI design and test group at IIEST, Shibpur, India. Dr Rahaman is a member of the VLSI Society of India (VSI), the IEEE, the IEEE Computer Society, and ACM Sigda. He is regular reviewer of IEEE TCAD, IEEE TVLSI, IEEE TC, and ACM TODAEs. He served on the conference committees of VLSI Design, VDAT, ATS, ISED, ISPD etc. E-mail: [email protected]