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Review Articles

An Approach for Detection and Localization of Missing Gate Faults in Reversible Circuit

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References

  • R. Landauer, “Irreversibility and heat generation in the computing process,” IBM J. Res. Dev., Vol. 5, pp. 183–191, 1961. doi: 10.1147/rd.53.0183
  • P. W. Shor, “Algorithms for quantum computation: discrete logarithms and factoring,” Found. Comput. Sci., 124–134, 1994.
  • C. H. Bennett, “Logical reversibility of computation,” IBM J. Res. Dev., Vol. 17, pp. 525–532, 1973. doi: 10.1147/rd.176.0525
  • T. Toffoli. “Reversible computing,” MIT Lab for Computer Science, Technical memo MIT/LCS/TM-151, 1980.
  • R.P. Feynman, “Quantum mechanical computers,” Found. Phys., Vol. 16, pp. 507–531, 1986. doi: 10.1007/BF01886518
  • E. Fredkin, and T. Toffoli, “Conservative logic,” Int. J. Theor. Phys., Vol. 21, pp. 219–253, 1982. doi: 10.1007/BF01857727
  • B. Kane, “A silicon-based nuclear spin quantum computer,” Nature, Vol. 393, pp. 133–137, 1998. doi: 10.1038/30156
  • K. Fazel, M. Thornton and J. E. Rice, “ESOP-based Toffoli gate cascade generation,” in IEEE PACRIM, Citeseer, 2007, pp. 206–209.
  • R. Wille, and R. Drechsler, “BDD-based synthesis of reversible logic for large functions,” DAC, pp. 270–275, 2009.
  • K. Ramasamy, R. Tagare, E. Perkins, and M. Perkowski, “Fault localization in reversible circuits is easier than for classical circuits,” in Proceedings of International Workshop on logic and synthesis, Temecula, CA, 2004.
  • A. Chakraborty, “Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays,” in Proceedings of VLSI design, Kolkata, 2005, pp. 249–254.
  • H. Rahaman, D. K. Kole, D. K. Das, and B. B. Bhattacharya, “Fault diagnosis for missing-gate fault (SMGF) model in reversible quantum circuits,” Computers & Electrical Engineering, Vol. 37, pp. 475–485, 2011. doi: 10.1016/j.compeleceng.2011.05.005
  • B. Mondal, D. K. Kole, H. Rahaman, and D. K. Das, “Generator for test Set Construction of SMGF in reversible circuit by Boolean difference method,” in Proceedings of Asian Test Symposium, Hangzhou, 2014, pp. 68–73.
  • C. Bandyopadhyay, D. Roy, D. K. Kole, K. Datta, and H. Rahaman, “ESOP-based synthesis of reversible circuit using improved cube list,” In 2013 International Symposium on Electronic System Design, IEEE, Singapore, 2013, pp. 26–30.
  • J. Mondal, D. K. Das, D. K. Kole, H. Rahaman, and B. B. Bhattacharya, “On designing testable reversible circuits using gate duplication,” in International Symposium on VLSI Design and Test, 2013, pp. 322–329.
  • D. K. Kole, H. Rahaman, D. K. Das, and B. B. Bhattacharya, “Derivation of optimal test set for detection of multiple missing-gate faults in reversible circuits,” in Proceedings of Asian test Symposium, Shanghai, 2010, pp. 33–38.
  • S. N. Mahammad, S. K. S. Hari, S. Shroff, and V. Kamakoti, “Constructing online testable circuits using reversible logic,” in International Symposium on VLSI Design and Test, 2006, pp. 373–383.
  • J. P. Hayes, I. Polian, and B. Becker, “Testing for missing-gate faults in reversible circuits,” in Proceedings of Asian Test Symposium, Kenting, 2004, pp. 100–105.
  • M. Perkowski, J. Biamonte, and M. Lukac, “Test generation and fault localization for quantum circuits,” in Proceedings of International Symposium on Multi-Valued logic, Calgary, BC, 2005, pp. 62–68.
  • I. Polian, J. P. Hayes, T. Fienn, and B. Becker, “A family of logical fault models for reversible circuits,” In Proceedings of Asian Test Symposium, Calcutta, 2005, pp. 422–427.
  • K. N. Patel, J. P. Hayes, and I. L. Markov, “Fault testing for reversible circuits,” in IEEE VLSI Test Symposium, Napa Valley, CA, 2003, pp. 410–416.
  • M. Zamani, M. B. Tahoori, and K. Chakrabarty, “Ping-pong test: Compact test vector generation for reversible circuits,” in IEEE VLSI test Symposium, Hyatt Maui, HI, 2012, pp. 164–169.
  • H. Rahaman, D. K. Kole, D. K. Das, and B. B. Bhattacharya, “On the detection of missing-gate faults in reversible circuits by a universal test set,” in IEEE VLSI design, 2008, pp. 163–168.
  • B. Mondal, C. Bandyopadhyay, D. K. Kole, J. Mathew, and H. Rahaman, “Diagnosis of SMGF in ESOP based reversible logic circuit,” in Proceedings IEEE International Symposium on Electronic System Design, Surathkal, Dec. 2014, pp. 89–93.
  • D. P. Vasudevan, P. K. Lala, and J. P. Parkerson, “Online testable reversible logic circuit design using NAND blocks,” in International Symposium on Defect and Fault-Tolerance in VLSI Systems, Cannes, 2004, pp. 324–331.
  • D. P. Vasudevan, P. K. Lala, D. Jia, and J. P. Parkerson, “Reversible logic design with online testability,” IEEE Trans. Instrum. Meas., Vol. 55, pp. 406–414, 2006. doi: 10.1109/TIM.2006.870319
  • S. N. Mahammad, and K. Veezhinathan, “Constructing online testable circuits using reversible logic,” IEEE Trans. Instrum. Meas., Vol. 59, pp. 101–109, 2010. doi: 10.1109/TIM.2009.2022103
  • R. Wille, D. Grosse, L. Teuber, G. W. Dueck, and R. Drechsler, “Revlib: an online resources for reversible functions and reversible circuits,” in 38th ISMVL, Dallas, TX, 2008, pp. 220–225.

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