High-Performance 3D Mesh-Based NOC Architecture Using Node-Layer Clustering

Abstract

Network-on-chip (NOC) architectures are being extensively employed following the growing number of cores in such networks as well as a rising trend in power/energy consumption and latency development. Proper NOC architectures can thus significantly contribute to the performance of these networks. Accordingly, a new architecture is proposed in this paper to decrease network diameter. A new particular topological structure is also presented based on node-layer clustering algorithm (NLCA) together with several rules for the main node as cluster-head (CH). A deadlock-free routing is subsequently suggested using this topology. To examine the effect of the given architecture on algorithm speed, the Scalable Universal Matrix Multiplication Algorithm (SUMMA) is further implemented and evaluated. Upon a decrease in the network diameter, the simulation results indicate a 10% improvement in energy consumption, 5.3% growth in network latency, and 20% enhancement in throughput as the given architecture is utilized. Moreover, SUMMA is employed in which a better cost in the proposed architecture can be established compared with its counterparts.

KEYWORDS:

• Clustering
• De Bruijn graph
• Network-on-chip
• Routing
• Topology

Additional information

Notes on contributors

Navid Habibi

Navid Habibi received his MS degree in computer engineering in Islamic Azad University of Tabriz Science and Research Branch, 2012. He is currently PhD student in Islamic Azad University in Iran South Tehran branch. He is a lecturer with Tehran Universities. His interests are in field of network on chip optimization and low power interconnections. Email: [email protected]

M. Reza Salehnamadi

Mohammad Reza Salehnamadi received BTech degree in electronic engineering from Science and Industrial University of Iran, Tehran, Iran in 1986 and MTech degree in communication systems from Industrial University of Isfahan, Isfahan, Iran, in 1988, and PhD in computer system architecture and hardware from Azad University of Iran, Science and Research Branch, Tehran, Iran in 2002. He is currently a faculty member of Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran. His researches fields are in computer architecture, NOC and parallel processing.

Ahmad Khademzadeh

Ahmad Khademzadeh received the BSc degree in applied physics from Ferdowsi University, Mashhad, Iran, in 1969, and the MSc and PhD degrees in digital communication and information theory and error control coding from the University of Kent, Kent, UK. He is currently the head of Education and National Scientific and International Scientific Cooperation Department, Iran Telecom Research Center (ITRC), Tehran, Iran. He was the head of Test Engineering Group and the director of Computer and Communication Department, ITRC. He is also a lecturer with Tehran Universities and is a Committee Member of the Iranian Electrical Engineering Conference Permanent Committee. Prof KhademZadeh was selected as the national outstanding researcher of the Iran Ministry of Information and Communication Technology. Email: [email protected]