Image Multiplication Using Novel 4:1 Approximate Compressor*

Abstract

Energy-efficient designs are the need of the hour for signal and image processing applications that are error-tolerant. The paper proposes a new 4:1 approximate arithmetic-based compressor developed by analyzing the probability-based tactics that have a higher degree of precision when implemented. Approximate $n\times n$ multiplier is designed using the proposed varying probability-based compressors. To validate the effectiveness of the new compressor, a $16\times 16$ multiplier is designed. The $n\times n$ bit multiplier will have $2n$ columns of partial products(PP), in which the least significant n−1 columns are designed using the novel approximate 4:1 compressor and most n + 1 columns are designed with the exact compressor. The results of the 16-bit multiplier are superior to the performance of the exact multiplier in terms of power, area, power-delay-product (PDP), and area-delay-product (ADP) typically by $39\mathrm{\%}$, $20\mathrm{\%}$, $44\mathrm{\%}$, and $26\mathrm{\%}$ respectively for Design 1 and $14\mathrm{\%}$, $24\mathrm{\%}$, $30\mathrm{\%}$, and $21\mathrm{\%}$, respectively for Design 2. The Peak Signal to Noise Ratio(PSNR), Mean Square Error(MSE), and Structural Similarity Index Measure(SSIM) for the output images processed by new approximate multipliers are acceptable when compared with precision and energy.

Keywords:

• Approximate 4:1 compressor
• Image processing hardware
• Probability-based compressor
• Error-tolerant applications

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Saranya Karunamurthi

Saranya Karunamurthi is an assistant professor, department of EEE at Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu. India. She completed her BE in The department of EEE at SKCET, Coimbatore under Anna University. She completed her ME in the department of Applied Electronics at Government College of Technology, Coimbatore. Her research interests are VLSI design, analog circuits, reversible circuits, and ASIC implementation. Email: [email protected]

Bhaskara Rao Jammu

Bhaskara Rao Jammu received his BTech from Andhra University. He received his master's from MNNIT, Allahabad and a PhD from NIT Rourkela. He has authored more than 10 research papers at National and International Levels. He worked as an ASIC design engineer in Aricent Technologies from 2006 to 2009. Currently, he is working as an associated professor in the department of ECE, GVP COE(A). He filed two Indian patents in the field of electronics. His research interests are approximate computing, evolvable hardware, biomedical image processing, artificial intelligence, and FPGA implementations.

Nalini Bodasingi

Nalini Bodasingi has been working as an assistant professor at JNTUGV since 2013. She received her PhD from JNTU Kakinada in the field of biomedical imaging & VLSI architectures. She has authored more than 10 research papers at the National and International Levels and guided three PhD Scholars. Currently, she is heading the department of ECE while also holding various posts at JNTUGV, including deputy warden, cultural coordinator, and officer in charge of examinations. She filed two Indian patents in the field of electronics. She holds a senior IEEE membership. Her areas of interest in research include biomedical image processing, artificial intelligence, approximate computing, evolvable hardware, and FPGA implementations. Email: [email protected]

Sreehari Veeramachaneni

Sreehari Veeramachaneni is a faculty member in the department of Electronics and Communication Engineering at Gokaraju Rangaraju Institute of Engineering and Technology,Hyderabad, India. He received his PhD degree from the International Institute of Information Technology Hyderabad. He is a reviewer of several IEEE/Springer/Elsevier journals. His research interests include arithmetic circuits approximate computing hardware security memory design, data converters, analog VLSI design, and low power VLSI. Email: [email protected]

Noor Mahammad S

Noor Mahammad S is currently working as a faculty in the Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, Chennai, India. He received a PhD in computer science and engineering from Indian Institute of Technology Madras. His research interests are reconfigurable computing, computer architecture, software for VLSI design, and network system design. Email: [email protected]