Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

Abstract

This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary I_ON/I_OFF ratio of 2.33 × 10¹³, with an I_OFF of 6.25 × 10⁻¹⁹A/µm, and decent I_on of 1.46 × 10⁻⁵A/µm along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.

KEYWORDS:

• Dual gate
• Dual source
• Subthreshold swing (SS)
• Tunnel field-effect transistor (TFET)
• Tunneling

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

P. Ghosh

P Ghosh received her Btech degree in electronics and telecommunication engineering from KIIT University, Bhubaneswar, Odisha, India, in 2015 and Mtech degree in electronics and communication engineering from National Institute of Technology, Meghalaya, India, in 2017. She received her PhD degree in electronics and communication engineering from National Institute of Technology, Silchar, India, in 2021. She is currently working as an assistant professor at the Department of Electronics and Communication Engineering, Indian Institute of Information Technology Ranchi, Ranchi, India. Her areas of interest are simulation and modelling of semiconductors, biosensors, and optical sensors. Corresponding author. Email: [email protected]

S. Pratap

S Pratap received his Btech degree in electronics and communication engineering from Indian Institute of Information Technology Ranchi, Ranchi, Jharkhand, India, in 2023. His areas of interest are simulation and modelling of semiconductor devices and biosensors. Email: [email protected]

S. Tripathi

S Tripathi received his Btech degree in electronics and communication engineering from Indian Institute of Information Technology Ranchi, Ranchi, Jharkhand, India, in 2023. His areas of interest are microelectronics, VLSI, modelling of semiconductors and optical sensors. Email: [email protected]

K. Yashwanth

K Yashwanth received his Btech degree in electronics and communication engineering from Indian Institute of Information Technology Ranchi, Ranchi, Jharkhand, India, in 2023. His area of interests are simulation modelling of semiconductors, digital circuit design, and microelectronics. Email: [email protected]