Design of Silicon Core Coaxial TSVs to Reduce Crosstalk Effects for 3D IC Applications

Abstract

This paper presents the effectiveness of the copper (Cu)-based coaxial through silicon vias (CTSVs) to reduce crosstalk noise and propagation delay. In the proposed CTSVs, the polymer liners are used as insulating material which cancels the crosstalk functional failures. The impacts of the proposed CTSVs on the electrical performance are noticed for different parameters and properties of the material. Simulations of the proposed CTSVs are executed using the standard HSPICE and SYMICAD tools. The results indicated that the effects of crosstalk are reduced using the polymer liners instead of silicon dioxide (SiO2) liners in the proposed CTSVs. The electrical performances of the proposed CTSVs are investigated for various thicknesses of Cu and BCB. Furthermore, a comparative study has been carried out for the SiO2 and benzocyclobutene (BCB) liners. It is observed that BCB liner-based CTSVs crosstalk noise and delay values are reduced by up to 25.06% and 27.8% compared to the SiO2 liner-based TSVs.

KEYWORDS:

• Crosstalk
• Electrical characterization
• Equivalent circuit model
• Integrated circuits
• Polymer liners
• Through silicon VIAs

Disclosure statement

No potential conflict of interest was reported by the author(s).

Additional information

Notes on contributors

Krishna Pal

Krishna Pal received the Mtech degree from Malaviya National Institute of Technology (MNIT) Jaipur, in 2021 and currently pursuing PhD at IIIT Sri City in the area of VLSI design. Corresponding author. Email: [email protected]

Bheemappa Halavar

Bheemappa Halavar received the PhD degree from National Institute of Technology Karnataka Surathkal in 2020. He is currently working as an assistant professor in the computer science engineering group, at IIIT Sri City. His current research interests are Network on chips (NoC)-system architecture, high-performance computing, and named data networking. Email: [email protected]

V. Ramesh Kumar

V Ramesh Kumar received his Mtech degree from National Institute of Technology Hamirpur, in 2010 and PhD degree from Indian Institute of Technology Roorkee, in 2016. He is currently working as an assistant professor in the ECE Group, at IIIT Sri City. His current research interests include modelling on-chip interconnects, CNT interconnects, QCA circuit design, and multi-valued logic design. Email: [email protected]