Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing

Abstract

The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thorough investigation of a novel 1-bit full adder circuits was conducted, covering their design, analysis, and optimization for minimizing their power consumption and delay while maintaining their robustness and functionality. The design also introduces modified XOR and XNOR gates as crucial components. The proposed circuit was simulated using Cadence Virtuoso tool with 90-nm GPDK CMOS technology. To evaluate the proposed adder, comparisons were made with several well-known adder designs based on power consumption, speed, and power delay product. The proposed hybrid full adder improved power delay product by 20.6% to 69.4% and reduced worst-case propagation delay by 16.6% to 63.5% compared to prior designs in the literature. This study's findings offer useful insights into digital circuit design and can contribute to the development of low-power, high-performance full adder circuits.

Keywords:

• CMOS
• CPL
• Full adder
• NMOS
• PMOS
• XOR-XNOR

Disclosure statement

No potential conflict of interest was reported by the author(s).

DATA AVAILABILITY

Data supporting findings available within the research paper.

Additional information

Notes on contributors

Satvik Goel

Satvik Goel earned his BTech degree in 2023 from Madan Mohan Malaviya University of Technology, Gorakhpur.His primary area of expertise lies in VLSI circuit design. Email: [email protected]

Saurabh Kumar

Saurabh Kumar (Corresponding author) received a BE degree in electronics and communication engineering from Bapuji Institute of Engineering and Technology, Davangere, Karnataka, India, in 2007. He received his MTech degree from Amity University, Noida, Uttar Pradesh, India, in 2012. He is currently pursuing a PhD degree from Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India. His research interests include microelectronics, VLSI digital and analog circuit design, optoelectronics, and solid-state device modelling. Corresponding author. Email: [email protected]

Ritam Tripathi

Ritam Tripathi graduated with a BTech degree in the year 2023 from Madan Mohan Malaviya University of Technology, Gorakhpur. He possesses a strong passion for VLSI. Email: [email protected]

Shivansh Bajpai

Shivansh Bajpai obtained his BTech degree in electronics and communication engineering from Madan Mohan Malaviya University of Technology in 2023. His research interest is in VLSI digital circuit design. Email: [email protected]

Rahul Soni

Rahul Soni earned his BTech degree in the year 2023 from Madan Mohan Malaviya University of Technology, Gorakhpur. His research interests are in VLSI digital and analog circuit design. Email: [email protected]

R.K. Chauhan

Rajeev Kumar Chauhan received the ME degree in control and instrumentation from the MNREC-Allahabad University (presently MNNIT), Allahabad, Uttar Pradesh, India, in 1993. He received a PhD degree in electronics engineering from Indian Institute of Technology (IITBHU), Varanasi, Uttar Pradesh, India, in 2002. He served as visiting professor in the Department of ECE, Faculty of Technology, Addis Ababa University, Ethiopia, from Dec-2003 till July 2005. He is currently a professor with the Electronics and Communication Engineering Department at the Madan Mohan Malaviya Universityof Technology, Gorakhpur, Uttar Pradesh, India. His research interests include microelectronics, VLSI, device modelling, microstrip antenna, and filters. Email: [email protected]