Operational planning and control of semiconductor wafer production

Abstract

Due to increased competition, semiconductor manufacturing has received considerable research attention over the last few decades. As a result, several optimisation and heuristic solution procedures are available to solve a variety of operational planning and control problems arising in semiconductor wafer manufacturing. This paper provides a glimpse into the evolution of the operational planning and control problems in semiconductor wafer production and possible approaches for their solution. It briefly introduces the current operational planning and control problems being solved and the approaches being taken to solve them (optimally or approximately). The paper concludes with some fruitful directions for future research.

Keywords:

• Production and operational planning and control
• Production scheduling
• Semiconductor wafer manufacturing
• Future research directions

1. Introduction

Semiconductors have made their way into most aspects of everyone's daily life. The number of applications and the market demand for integrated circuits have increased dramatically since the invention of the transistor in 1948. Integrated circuits are at the heart of most of our modern conveniences including automobiles, personal computers, mobile phones, and television sets. Increased demand has lead to increased competition in the market place. No longer is it sufficient only to design a good product; today, a semiconductor company must be able to manufacture the product at a reasonable cost and deliver it on time.

Semiconductor manufacturing comprises four main steps: wafer fabrication, probe or sort, assembly or packaging, and final test. In wafer fabrication, the integrated circuits (ICs) are fabricated layer by layer on silicon wafers. After wafer fabrication, the wafers are sent to the sort or probe step where electrical probes are connected to each IC on the wafer to determine whether or not they are functional. The good ICs are identified and an electronic map of the wafer is made so that only the good ICs are put into a package at the next step, which is called assembly or packaging. The specific package that an IC is put into depends on its ultimate use. Finally, the packaged ICs go through a series of test operations to ensure that only fully functional ICs are delivered to the customer.

This paper provides a glimpse of the developments in solving the operational planning and control problems arising in semiconductor wafer production. Since the purpose of this paper is to provide a glimpse into various research activities arising in the operational planning and control of semiconductor manufacturing and to introduce this special issue, references cited are neither exhaustive nor complete. They are cited for convenience of the reader to locate some additional readings if desired. After briefly discussing the wafer production process and the operational planning and control issues in wafer manufacturing and fabrication, current state of research is introduced. Subsequently, several plausible and fruitful directions for future research are outlined.

2. The wafer production

Manufacturing of semiconductors starts with the production of wafers which are mainly made from silicon substrates. The production of VLSI products and more specifically, processor chips, greatly depend on the chemical purity and near-perfect crystalline properties of wafers. Therefore, the production of silicon wafers has achieved a high degree of intricacy with many complex phases like raw material refining, silicon ingot growing, peripheral grinding, ingot slicing into wafers, wafer bevelling, lapping and etching, heat treatment, polishing, ultra-pure water cleaning and finally, inspection, packaging and shipping. The margins of chip manufacturing companies greatly depend on yields which are a function of the semiconductor die geometry, size and also of the wafer diameter and purity. Defects on wafers translate into lower yields of the final chips and thus the importance of accurate control in the wafer production.

Wafer fabrication is the most costly and time consuming of the semiconductor manufacturing steps. The cost of a new wafer fabrication facility (or ‘wafer fab’) is approaching $4 billion and it generally takes 4 to 6 weeks to fabricate an entire silicon wafer containing ICs. Since customers now have many options as to who will manufacture their ICs, semiconductor manufacturers have had to increase their efforts to provide high-quality, on-time deliveries of affordable products to their customers. Today's wafer fabs have been forced to become increasingly conscious of their due date delivery performance, as dissatisfied customers now have a number of other manufacturers to turn to, should they need to find another supplier.

There are a number of different types of wafer fabs today, including fabs that produce ICs that are essentially commodities (i.e. for general marketplace consumption, such as microprocessors) and wafer fabs that produce application-specific integrated circuits (ASICs) for a wide array of customers. While a commodity wafer fab typically produces large quantities of a few different product types (high-volume manufacturing), ASIC fabs generally produce lower volumes of many different products (ASIC manufacturing). In both types of wafer fab, semiconductor manufacturers strive to schedule the various orders (jobs) in their factory in such a way as to maximise on-time delivery to their customers. This maximises their chance of retaining customers and receiving subsequent orders due to their previous performance.

The cost of equipment in a new wafer fab is over 75% of the total factory capital costs according to the International Technology Roadmap for Semiconductors (ITRS 2005). Further, much of the equipment in a modern wafer fabs is on the ‘bleeding edge’ of technology and suffers from frequent occurrences of long tool failures or extensive preventive maintenance. This results in large variability in the time a job spends at a work station (machine) and ultimately, the time a job spends in the system (cycle time). Highly variable lot cycle times make accurate prediction of production cycle times almost impossible, resulting in longer customer lead-time commitments.

The ITRS indicates that in order to utilise this expensive equipment effectively, significant improvements in factory planning and scheduling are required. In addition to the cost pressures, today's highly competitive semiconductor markets place a greater emphasis on responsiveness to customer order lead times which must be both short and reliable to provide good delivery performance. This can be achieved through a combination of (a) good production planning, scheduling, and control and/or (b) using inventory to buffer customers against potential lengthy manufacturing delays. Due to high holding costs and potential product obsolescence, holding extra inventory is becoming less and less attractive to semiconductor manufacturers. Thus, they have become increasingly interested in using effective planning and scheduling techniques as a vehicle to achieve a competitive advantage.

3. Operational control of wafer production

The operational control (including planning and scheduling) of semiconductor manufacturing facilities is a very difficult problem, as these systems are among the most complex manufacturing environments encountered today. Uzsoy et al. (1992, 1994) provide an excellent description of the semiconductor manufacturing process, including discussions of production planning, scheduling, control, and fab performance evaluation. There are six main features that complicate the operational control of these systems: the large number of processing steps, re-entrant (recirculating) flows, batch-processing tools, random equipment failures, sequence-dependent tool setups, and the need for auxiliary resources (e.g. reticles) at some processing steps.

Most wafer fabs contain over 100 machines and often there are dozens of process flows, each with a very specific set of 300–500 processing steps. Semiconductor manufacturing machines are expensive, with some costing more than $18 million per unit. The cost of this equipment dictates that such expensive machines be shared by all lots requiring the particular processing operations provided by the machine. This is true even if the wafers are at different stages of the manufacturing process. It is not uncommon for a product to visit the same machine group more than 20 times during its manufacture (this is called re-entrant or recirculating flow). Thus, the manufacturing environment is different in several ways from both flow shops as well as job shops (Pinedo 2002). The main consequence of this re-entrant flow is that wafers at different stages in their manufacturing process flow have to compete with each other for the same machines. How this competition is resolved has a clear impact on fab performance measures. Although still in its infancy, there is some research in the use of re-entrant manufacturing in highly unreliable machines with applications to wafer fabrication as shown in Kumar et al. (2004).

Another complicating factor is that the nature and duration of the various operations in a semiconductor process flow widely vary. Some process step operations require 15 minutes or less to process a group or lot of silicon wafers, while others may require over 12 hours. Most of these long operations are batch processes wherein multiple lots are processed simultaneously. It is not uncommon for one-third of a fab's operations to be batch operations. Batch machines process multiple lots (typically one to six) simultaneously and then send the completed lots to tools that are capable of processing only one lot at a time. Some methods have been proposed in the literature for batching in the semiconductor industry (see Lee et al. 1992 and Fowler et al. 2000). The variability induced in the fab from batch-processing (batching) machines often leads to the formation of long queues in front of these single lot serial tools and ultimately a non-linear flow of products in the wafer fab. As of recently, the non-linear cycle times depending on lot size in wafer fabrication have also been discussed in Asmundsson et al. (2006).

There are some wafer fab machines, such as ion implanters, that require significant sequence-dependent setups (tool configuration changeovers). If the flow of product in the fab is not controlled properly, these tools can become production bottlenecks. Horng et al. (2000) provide some preliminary research on this topic. Finally, some processing steps require an auxiliary resource, such as a reticle in photolithography, in addition to the primary required machine in order to process the job properly. Since these auxiliary resources can be quite expensive, only a very limited number of them are typically purchased. Therefore, the primary challenge is to ensure that both the machine and the auxiliary resource are available at the same time for efficient job processing. A recent article by Diaz et al. (2005) discusses this problem in more detail. All of these factors described above combine to make the operational control of wafer fabs quite a challenging, difficult task.

4. Current research in wafer production

The aim of this special issue is to provide researchers and practitioners with the latest developments in the operational control aspects of wafer fabrication. In addition to this introductory paper, this special issue contains a total of eight papers that deal with important aspects such as wafer plant layout, inventory management, scheduling, and preventive maintenance.

When we first envisioned this special issue, we anticipated a set of survey papers covering the past, present, and future of operational planning and control issues in semiconductor wafer production. Instead, we received submissions that were as eclectic as those appearing in any randomly chosen issue of this journal. Thus, the papers that survived the rigorous review process and that are included in this special issue represent the current state of the art in semiconductor wafer production planning and control. The first two papers deal with the material handling and plant layout issues in semiconductor wafer shops. The next two papers concentrate on the capacity allocation and inventory management in wafer production. One paper deals with distributed production planning and control decision making by using multi-agent systems. The next two papers involve the analysis and solution of some scheduling problems in semiconductor plants. The final paper in this special issue deals with the design and selection of appropriate preventive maintenance scheduling policies to maximise throughput without adversely affecting other measures of performance.

As discussed in the previous section, one of the ultimate goals of operational planning and control is to reduce cycle time as much as possible. In order to do so, production systems need to be inexpensive to construct and efficient to operate. In the paper, ‘A literature survey on the design approaches and operational issues of automated wafer-transport systems for wafer fabs’, Jairo R. Montoya-Torres reviews existing research on various aspects of factory design, such as facility layout, automated material handling systems (AMHS) design and AMHS operational issues. When addressing the shop design topic, facility layout and material handling system design are two important and interconnected problems. Therefore, Montoya-Torres critically examines research studies related to these problems for the particular case of the Integrated Circuit (IC) semiconductor manufacturing industry and identifies emerging opportunities for future research. This analysis is useful to identify future research projects as well as some guidelines to solve practical problems.

Improving the layout of a wafer fabrication plant is the topic of the next paper by Boaz Golany, Alexey Gurevich and Emanuel Paz Puzailov. Their paper entitled ‘Developing a 3-D layout for wafer fabrication plants’ deals with wafer plants that handle the work-in-progress by automated storage/retrieval systems where the unfinished products are stored in three dimensions. Furthermore, this paper presents a radically new plant layout where different shop machines are also placed at different levels and cranes transport the products to and from various machines without restrictions in a three-dimensional space. Apart from savings in plant real estate, the proposed approach shows an improvement in overall throughput when compared to more traditional layouts.

In wafer production, capacity planning and control can affect the resulting cycle time. Due to different capabilities of existing technologies, several process window constraints need to be considered in capacity planning and allocation. Further, due to a need to improve the yield rate of wafer production, machine utilization constraint is often used as a control mechanism. The interaction of these two constraints complicates the problem of capacity planning and allocation. Therefore, in their paper, ‘Capacity allocation model for photolithography workstation with the constraints of process window and machine dedication’, Shu-Hsing Chung, Chun Ying Huang and Amy Lee propose an integer programming model to solve the capacity allocation problem with the objective of load leveling under the process window and machine utilization constraints. Using information from an actual wafer fab, the authors show that an acceptable solution can be obtained in reasonable computation time. The loading allocation resulting from their model, therefore, can be used for wafer lot release and dispatching of work to photolithography machines.

In semiconductor manufacturing, product performance often varies from the intended design specifications. In light of long manufacturing lead times, high demand uncertainty and short product life cycles, finding efficient supply and demand planning becomes extremely difficult. In order to tackle such problems, the next paper entitled, ‘Semiconductor Inventory Management with Multiple Grade Parts and Downgrading’, by Guillermo Gallego, Kaan Katircioglu and Bala Ramachandran considers the inventory management problem in a semiconductor production system that results in multiple grade parts where downward substitution (i.e. downgrading high grade products) is used to satisfy unmet demand for lower grade parts. By modelling it as an inventory cost minimization problem with service constraints and introducing the notion of a critical part, these authors propose two heuristics for determining near optimal build quantities in key stages of manufacturing. Their computational experiments show that a single period allocation scheme does not result in inventory performance deterioration in the multi-period stationary case.

In order to reduce the complexity of operational planning and control problems in semiconductor manufacturing, distributed solution heuristics are being explored in the literature. Since it is difficult and time consuming to collect the required information for using centralised algorithms in real-world wafer production, distributed algorithms working on local data are highly desirable. In their paper, ‘The FABMAS multi-agent-system prototype for production control of wafer fabs: Design, implementation, and performance assessment’, Lars Mönch, Marcel Stehli, Jens Zimmermann, and Ilka Habenicht show that the current and emerging developments in software agents enable the implementation of a distributed planning and control system for wafer manufacturing. They describe a three-layer hierarchically organized multi-agent-system prototype that is used for production control of semiconductor wafer fabrication facilities (wafer fabs) to minimise total weighted tardiness. Their implementation of the multi-agent system is based on the PROSA reference architecture for holonic manufacturing systems and allows for a distribution of the system on a computer cluster. Results of their computational experiments with the system prototype show that the proposed system outperforms the FIFO dispatching based approaches currently used in practice.

In the wafer fabrication facility, implanter workstations are often the bottleneck and hence must be effectively utilised as much as possible. However, because of the setup time required between the processing of batches, some productive time can be lost. Therefore, appropriate scheduling techniques are required to make effective schedule batches in face of setup times (Allahverdi et al. 1999, Cheng et al. 2000). In view of the NP-hard nature of such problems, Zaid Duwayri, Mansooreh Mollaghasemi, Dima Nazzal, and Ghaith Rabadi in their paper entitled ‘Scheduling setup changes at bottleneck workstations in semiconductor manufacturing’, develop a heuristic to schedule a given number of batches on a bottleneck machines to reduce cycle time. Their study focuses on developing a scheduling heuristic for ion implanters at Cirent Semiconductor (currently Agere Systems) in Orlando, Florida where implanters are considered to be a bottleneck workstation. Their scheduling heuristic aims at balancing workload levels for implanters processing jobs at different stages of the wafer production lifecycle. This is accomplished by first processing those jobs that contribute most to increasing inventory levels at the bottleneck workstation. Their simulation results show that the proposed heuristic performs better than exiting rules in terms of mean cycle time and work-in-process inventory, and better in terms of standard deviation of cycle time.

In addition to cycle time reduction, scheduling techniques for minimising weighted tardiness are quite important in practice. This is especially true when jobs are not available at the same time implying that jobs arrive at different times. For a batch processing machine, therefore, the problem is one of forming batches and scheduling these batches to minimise total weighted tardiness. In their paper, ‘A branch and bound algorithm to minimise total weighted tardiness on a single batch processing machine with ready times and incompatible job families’, Sarat K. Tangudu and Mary E. Kurz develop a branch and bound algorithm to solve this problem for a single batch processing machine with characteristics similar to those seen in the diffusion operation in semiconductor manufacturing. They also utilise dominance properties to increase the efficiency of the algorithm. Their computational results show that the proposed algorithm is capable of finding optimal solutions for problems with up to 32 jobs.

In order to accomplish the production plans created by various operational planning and control activities in wafer production, it is essential that the machines used be available as and when needed. However, in practice, machines do breakdown and need to be repaired. The number of maintenance personnel assigned to the maintenance and repair function affects the final cycle time. In fact, an appropriate design of maintenance personnel allocation can reduce the cycle time by 25% (Ignizio 2004). Further, appropriate preventive maintenance can decrease the failure of machines used to produce semiconductor wafers and hence reduce the cycle time. The last paper in this special issue, ‘Improving preventive maintenance scheduling in semiconductor fabrication facilities’ by Adolfo Crespo Marquez, Jatinder N. D. Gupta and James P. Ignizio applies continuous time Monte Carlo simulation to study and assess different preventive maintenance scheduling policies. The salient characteristic of this study is that advanced maintenance policies can be used to maximise the throughput of the wafer manufacturing process without affecting the usual availability of tools or machines. These authors suggest that by appropriately selecting a maintenance scheduling policy, throughput can be maximised without causing a deterioration in other performance measures. Their simulation results validate their suggestions and provide some practical means to design and operate appropriate preventive maintenance scheduling policies in semiconductor fabrication facilities.

5. Conclusions and directions for future research

This paper has provided a brief excursion into the developments in solving the operational planning and control problems arising in semiconductor wafer production. During the past three decades, semiconductor wafer fabrication research has seen an evolution from theoretical and abstract modelling to the development of models that more nearly match the conditions found in real-life wafer production systems. Recent advances in heuristic approaches, the availability of reasonably inexpensive high-speed microcomputers for nearly every researcher, and ongoing developments in integer programming software have resulted in optimal or near-optimal solutions for larger and more complex problems.

In spite of several developments, most operational planning and control problems related to semiconductor wafer production remain largely unsolved. The reported progress in operational control theory, while advancing at a rapid pace, is not appreciable to solve practical problems optimally and efficiently. Furthermore, there is a lack of integrative and interactive decision making in the field of production planning and control as many aspects of business practices are not included in the development of algorithms for specific problems. The future research directions suggested here are intended to bridge the gap between the development of theory and practical applications of theory. Three areas of research are identified: theoretical, computational, and empirical research.

5.1 Theoretical research

The development of operational planning and control techniques for semiconductor wafer production, particularly those related to scheduling, thus far are essentially curtailed enumeration schemes. For example, the dominance conditions developed (in combinatorial and branch and bound procedures) in scheduling depend on partial schedules that precede a job candidate. Theoretical research in scheduling theory should attempt to develop dominance conditions that are either independent of partial schedules that precede a job candidate or are such that a large number of partial schedules containing a lesser number of jobs are rejected quickly. For most practical problems, however, it is unlikely that dominance conditions independent of preceding and proceeding partial schedules can be developed since this would imply the existence of a polynomial bounded algorithm—a result which contradicts the well established results on the complexity of scheduling and related combinatorial problems.

The combinatorial analysis approach, however, can be specialised to develop polynomial-bounded algorithms for several special structure production planning and control problems if there is enough justification for special cases. For example, the unidirectional nature of workload found in several wafer production shops and the restrictive assumptions in flowshop research (Gupta 1979, Gupta 2002, Gupta and Stafford 2006) do imply some structural relationships among the processing times of various jobs on different machines. It is reasonable to deduce that the restrictive flowshop scheduling problem will have well established structural relationships which are situation dependent. Therefore, theoretical research should consider many more special cases of planning and control problems than have been considered before and develop efficient optimisation techniques for their solution. Simultaneously, more quick, perhaps dirty but reliable heuristic procedures should be developed. Consideration of hybrid heuristic approaches for these problems provides another fruitful area for future theoretical research.

As stated earlier in this paper, the production of wafers requires scheduling of jobs on a large number of machines where jobs re-enter processing several times after their being processed by subsequent machines. However, there is very little theoretical research to analyze and solve such problems with the notable exceptions of Mason et al. (2002), Mason et al. (2004) and Mason et al. (2005). Therefore, the development of models and solution procedures for solving re-entrant flowshop scheduling problems involving large number of machines would enhance the effectiveness and efficiency of semiconductor wafer production.

Much of existing research in operational planning and control of semiconductor wafer production makes use of simulation modelling to find solutions to practical problems. While useful to solve immediate problems, such studies do not provide any sense of the suboptimality of the solution implemented. Therefore, even though simulation studies are very useful in practice, mathematical models of various operational planning and control problems should be developed with a view to finding optimal, or near optimal, solutions. For the case of approximate solution procedures, worst-case and average-case performance bounds should be developed. In order to reduce the cycle time in wafer fabrication, waiting time for repairing the failed machines must be minimised. This requires the consideration of the appropriate spare part ordering policies to minimise waiting time which in turn reduces overall cycle time. Theoretical research is required to extend the reliability and availability models and to integrate them with mathematical programming approaches to find optimal spare-part ordering policies.

The measures of performance used in operational planning and control depend on such considerations as the interactions between scheduling, inventory, and plant layout. Theoretical research should quantify these interactions and develop general purpose models of operational planning, scheduling, and control problems and general purpose measures of performance. These general purpose models could then provide an insight and perhaps the directions, for the development of solution techniques for only a narrow range of measures of performance. In addition, they may provide a motivation for the practical use of the theoretical developments.

5.2 Computational research

The past three decades of operational planning and control research for wafer production have provided a panorama of techniques that claim to find acceptable solutions. However, a practical production planner still has difficulty in selecting an algorithm to solve a given planning and control problem. The computational research should consider such aspects as comparative efficiency of various algorithms for a specified problem with given data set. Thus, new measures of computational effort needed to solve a problem should be developed. At present, the effectiveness and/or efficiency of heuristic algorithms is an aspect that needs more attention. Often computational results are presented on the basis of average results, which represents a poor statistical practice (see Barr et al. 1995, Hooker 1995 and Rardin and Uzsoy 2001 among many other examples). However, the existing measures, average number of solutions examined and average computational time on one hand and the worst-case performance bounds on the other may be inappropriate measures for algorithm selection. In addition, artificial intelligence techniques, such as neural networks (Gupta et al. 2000) should be further exploited to select specific heuristics to be used for a given problem.

The mathematical programming approach to many operational planning and control problems seems to have been abandoned because of excessive computational burden and heuristic solution procedures are being developed instead. Recent advances in solving large-scale mathematical programming problems and the availability of approximate solution procedures for the integer programming problem may show that the mathematical approach can, in fact, be used to find realistic solutions with less computational effort. A comparative computational investigation of the mathematical programming techniques and other specifically designed procedures (exact and approximate) would be of immense value in indicating future research trends. In this regard, it may well turn out that heuristic solution procedures based on mathematical programming approaches provide better solutions than other heuristics specifically designed for a particular problem defined in a very narrow domain.

Finally, considering the sheer complexity of the operational planning and control problems in wafer fabrication, another interesting research topic is parallel computing. These techniques, which had a golden age in the late 1970s and 1980s, suffered from a range of problems, mainly dealing with the fact that parallel computing required dedicated and expensive machinery, which precluded a wide application of parallel methods. However, with modern threaded operating systems, together with the advent of inexpensive microprocessors which include hyperthreading or several parallel cores, computing in a parallel fashion might undergo a revival of youth. Other techniques like clustering mainstream microcomputers with available networks or grid technologies serve as a very fertile ground for parallel approaches. With these techniques, computationally intensive algorithms which have been designed with parallelisation in mind can be run across several cores in a single microcomputer or have the computing load distributed among the unused computing resources at a firm. All this will surely result in better solutions to more complex problems.

5.3 Empirical research

The mathematical developments in operational planning and control suffer from too much abstraction and too little application. Research in semiconductor fabrication seem to be motivated by what the researchers can achieve rather than what is important. As a result of this approach to research developments, practical use of available techniques is quite low. This questions their suitability. In spite of three decades of research in operational planning and control of wafer production, we don't know much about the exact nature of practical operational planning and control problems except that they exist and require frequent solutions. Perhaps we have over-emphasised the rigour in mathematical development at the cost of underemphasising the realism of problem formulation. Future research in operational planning and control should be inspired more by real life problems rather than problems encountered in mathematical abstractions.

For a realistic problem formulation, empirical research is necessary to understand the practical situations. Operational planning and control is only one of those areas where only a few case histories are available. Empirical research should answer such questions as: What is the maximum problem size encountered in practice? What specific situations give rise to what type of problems? What are the desired objectives of solving a problem? What is the nature of processing times and other problem parameters? How rigid (or flexible) are the operating policies? Empirical research, therefore, needs to include a survey of industrial planning and control practices and situations. Without such a survey, we may in fact spend another thirty years in solving problems that perhaps need no solutions, since they may be the wrong problems (from practical consideration). A first attempt at such a survey can be found in Pfund et al. (2006).

The above suggested research directions are not meant to replace the existing efforts in solving operational planning and control problems found in wafer production. Rather, they are designed to provide a framework for viewing several problems and the contributions of various research efforts in solving practical problems. The recent developments in supply chain management, Internet, and e-commerce have created new and complex planning, control, scheduling and co-ordination problems that we have just begun to understand. Therefore, we need to diversify our research efforts to include these new and emerging problems. Along with these research efforts, a survey of industrial operational control problems and practices would aid in the identification and clear definition of various problems encountered in practice and the need to solve such problems. This alone can provide the needed impetus to bridge the gap between theoretical developments and industrial practices in operational planning, scheduling and control.

Acknowledgments

The completion of this special issue has involved hard work and contributions by several people in addition to the authors of the papers. Professor Stephen Childe, Editor-in-Chief of the Production Planning & Control journal originally invited one of the guest editors (Jatinder Gupta) to edit this special issue. He has worked closely with us to get this issue to publication. His experience, dedication, and work has improved the quality of this issue. The large number of submissions for this issue resulted in our calling on the services of many referees. We therefore thank these anonymous individuals for helping with the review process. They each spent many hours in reviewing, critiquing, and re-reviewing the many papers considered for this issue. Without their efforts, this issue could not have been completed. We are also grateful to those authors whose papers could not be included in this issue for a variety of reasons. We trust that their work will eventually appear elsewhere in the literature. Finally, we are thankful to our respective department chairs and college deans for allowing us to work on this special issue.