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Abstract
We discuss the correlation between intermetallic dielectric (IMD) processes and electrical properties of fully integrated ferroelectric cells. The best IMD scheme for higher density FRAM devices is proposed regarding gap-filling properties of narrow metal pitches and electrical characteristics. The used oxides were i)HDP, ii)HDP/POX, and iii)PSG/SOG/USG. HDP possesses good gap-filling characteristics due to the simultaneous application of deposition and etching. However it generates large plasma loads to the wafer, resulting in an undesired degradation of the 2Pr values. The HDP/POX stacks employ an additional POX oxide buffer layer in order to minimize damage due to the HDP deposition process, but the application of the double stack structure shows the same degradation as the HDP-only scheme. However, PSG/SOG/USG stack showed good gap-filling characteristics as well as lower 2Pr degradation. In the triple stack, PSG and USG act as a main IMD layer and as an oxide buffer for SOG coating, respectively. In addition, a definite voltage separation exists between data “1” and data “0” when PSG/SOG/USG is used as IMD, which demonstrates good sensing margin for high-density FRAM scheme. In conclusion, we successfully developed a novel 32Mb FRAM with 1T1C COB structure which was successfully fabricated by using a new IMD scheme of USG/SOG/PSG.