Integration of MOCVD SBT Stacked Ferroelectric Capacitors in a 0.35 μ m CMOS Technology

Abstract

This paper reports on the integration of MOCVD SBT based stacked ferroelectric capacitors in a 0.35 μ m CMOS technology for embedded FeRAM, using a ferroelectric capacitor (FeCap) that is scalable to a 3D configuration. The electrical parameters of the CMOS devices with and without FeCap integration are presented. No significant shifts of the CMOS characteristics are noticed after FeCap integration. Also the effects of the CMOS processing on the FeCaps are discussed. There is no degradation of the hysteresis loops of the FeCaps throughout the CMOS back-end-of-line processing, which proves that the integrated encapsulation layer effectively prevents any hydrogen induced damage. Another key element in the successful integration of stacked ferroelectric devices is the conductive oxygen barrier, which protects the plugs from oxidation. A low contact resistance and a high yield are obtained on plug contacts covered by the oxygen barrier. Also damage free etching is a critical issue in FeRAM integration. Excellent results are presented for the etch process to form the contacts to the electrodes.

Keywords:

• FeRAM
• integration
• SBT
• MOCVD
• 3D
• oxygen barrier
• hydrogen barrier

ACKNOWLEDGEMENTS

The authors would like to thank H. Vander Meeren, F. Vleugels and M. Willegems of IMEC for technical assistance during wafer processing, and acknowledge the partial financial support through the IST project 2000-30153 FLEUR and ESA project ESTEC/CONTRACT No. 13579/99/NL/PB.