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Integrated Ferroelectrics
An International Journal
Volume 89, 2007 - Issue 1
28
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SECTION J: DEVICE PROCESS INTEGRATION/RELIABILITY (FERRO-, PIEZO-, PYRO-ELECTRICS)

A NOVEL ATE (ADDITIONAL TOP-ELECTRODE) SCHEME FOR A 1.6 V FRAM EMBEDDED DEVICE AT 180 NM TECHNOLOGY

, , , , , , , , , , & show all
Pages 106-115 | Received 31 May 2006, Published online: 12 Oct 2011
 

ABSTRACT

We developed a 1.6 V FRAM embedded device by successfully implementing a 100 nm MOCVD-PZT capacitor with a SrRuO3 electrode and a novel additional top electrode (ATE). ATE was used for preventing hydrogen-reduction damage or metal substance damage, arising from direct application of Al or W to top electrode. In spite of excellent reliability and wide sensing window of the memory, we found that there was a problem of lift-off of the ATE layer after full integration, leading to bit failure of the product. In order to eliminate the lift-off, we developed a new ATE scheme not only by using a compressive capping- oxide layer but by improving conformal deposition of ATE. The failed bits that appear as a tail of charge distribution were cleared even under a reliability test, a bake for 100 hours at 150°C. As a result, yield loss of the device was greatly reduced.

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