Efficient routing in network-on-chip for 3D topologies

References

• Benini, L., & De Micheli, G. (2002). Networks on chips: A new SoC paradigm. Computer, 35(1), 70–78. doi:10.1109/2.976921
   Web of Science ®Google Scholar
• Bonabeau, E., Dorigo, M., & Theraulaz, G. (1999). Swarm intelligence: From natural to artificial systems. New York, NY: Oxford University Press.
   Google Scholar
• Chiu, G. M. (2000). The odd-even turn model for adaptive routing. IEEE Transactions on Parallel and Distributed Systems, 11(7), 729–738. doi:10.1109/71.877831
   Web of Science ®Google Scholar
• Di Caro, G., & Dorigo, M. (1998). Antnet: Distributed stigmergetic control for communications networks. Journal of Artificial Intelligence Research, 9, 317–365.
   Web of Science ®Google Scholar
• Dick, R. (2008). Embedded system synthesis benchmarks suites (E3S). Retrieved from www. ece. northwestern. edu/dickrp/e3s/
   Google Scholar
• Dorigo, M., Birattari, M., & Stutzle, T. (2006). Ant colony optimization. IEEE Computational Intelligence Magazine, 1(4), 28–39. doi:10.1109/CI-M.2006.248054
   Web of Science ®Google Scholar
• Dorigo, M., Maniezzo, V., & Colorni, A. (1996). Ant system: Optimization by a colony of cooperating agents. IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, 26(1), 29–41. doi:10.1109/3477.484436
   PubMed Web of Science ®Google Scholar
• Duato, J. (1993). A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Transactions on Parallel and Distributed Systems, 4(12), 1320–1331. doi:10.1109/71.250114
   Web of Science ®Google Scholar
• Duato, J., Yalamanchili, S., & Ni, L. (2003). Interconnection networks (The Morgan Kaufmann Series in Computer Architecture and Design). San Francisco, CA: Morgan Kaufmann.
   Google Scholar
• Duzett, B., & Buck, R. (1992, October). An overview of the nCUBE 3 supercomputer. In Fourth symposium on the frontiers of massively parallel computation, 1992 (pp. 458–464). doi:10.1109/FMPC.1992.234880
   Google Scholar
• Esser, R., & Knecht, R. (1993). Intel paragon xp/s – Architecture and software environment. In H.-W. Meuer (Ed.), Supercomputer ′93 (pp. 121–141). Berlin: Springer-Verlag. doi:10.1007/978-3-642-78348-7_13
   Google Scholar
• Glass, C. J., & Ni, L. M. (1992). The turn model for adaptive routing. In ACM SIGARCH computer architecture news (Vol. 20, pp. 278–287). New York, NY: ACM. doi:10.1145/146628.140384
   Google Scholar
• Goss, S., Aron, S., Deneubourg, J., & Pasteels, J. (1989). Self-organized shortcuts in the argentine ant. Naturwissenschaften, 76, 579–581. doi:10.1007/BF00462870
   Web of Science ®Google Scholar
• Grassé, P. (1959). La reconstruction du nid et les coordinations interindividuelles chez bellicositermes natalensis et cubitermes sp. la théorie de la stigmergie: Essai d’interprétation du comportement des termites constructeurs. Insectes Sociaux, Birkhäuser Basel, 6, 41–80. doi:10.1007/BF02223791
   Google Scholar
• Hennessy, J. L., & Patterson, D. A. (2011). Computer architecture: A quantitative approach (5th ed.). San Francisco, CA: Morgan Kaufmann.
   Google Scholar
• Kessler, R. E., & Schwarzmeier, J. L. (1993). CRAY T3D: A new dimension for cray research. Compcon spring’93, digest of papers, pp. 176–182.
   Google Scholar
• Marcon, C., Calazans, N., Moreno, E., Moraes, F., Hessel, F., & Susin, A. (2011). CAFES: A framework for intrachip application modeling and communication architecture design. Journal of Parallel and Distributed Computing, 71(5), 714–728. doi:10.1016/j.jpdc.2010.10.002
   Web of Science ®Google Scholar
• MathWorks. (2008). MATLAB Version 7.7.0 (R2008b). Natick, MAs: The MathWorks.
   Google Scholar
• Moraes, F., Calazans, N., Mello, A., Moller, L., & Ost., L. (2004). Hermes: An infrastructure for low area overhead packet-switching networks on chip. Integration, the VLSI Journal, 38(1), 69–93. doi:10.1016/j.vlsi.2004.03.003
   Web of Science ®Google Scholar
• Mourelle, L., Ferreira, R., & Nedjah, N. (2010). Migration selection of strategies for parallel genetic algorithms: Implementation on networks on chips. International Journal of Electronics, 97(10), 1227–1240. doi:10.1080/00207217.2010.512021
   Web of Science ®Google Scholar
• Nedjah, N., Silva, M., & Mourelle, L. (2009a). Efficient mapping of an image processing application for a network-on-chip based implementation. International Journal of High Performance Systems Architecture, 2(1), 46–57. doi:10.1504/IJHPSA.2009.030098
   Google Scholar
• Nedjah, N., Silva, M., & Mourelle, L. (2009b). Optimal IP assignment for efficient NoC-based system implementation using NSGA-II and microGA. Ijcis, 2(2), 115–123. doi:10.2991/ijcis.2009.2.2.2
   Web of Science ®Google Scholar
• Nedjah, N., Silva, M., & Mourelle, L. (2011). Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization. Journal of Systems Architecture: The EUROMICRO Journal, 57(1), 79–94. doi:10.1016/j.sysarc.2010.07.004
   Web of Science ®Google Scholar
• Nedjah, N., Silva Junior, L., & Mourelle, L. (2013). Congestion-aware ant colony based routing algorithms for efficient application execution on Network-on-Chip platform. Expert Systems with Applications, 40(16), 6661–6673. doi:10.1016/j.eswa.2013.06.005
   Web of Science ®Google Scholar
• Ni, L. M., & McKinley, P. K. (1993). A survey of wormhole routing techniques in direct networks. Computer, 26(2), 62–76. doi:10.1109/2.191995
   Web of Science ®Google Scholar
• Ozturk, O., & Demirbasa, D. (2010). Heterogeneous network-on-chip design through evolutionary computing. International Journal of Electronics, 97(10), 1139–1161. doi:10.1080/00207217.2010.512020
   Web of Science ®Google Scholar
• Seo, D., Ali, A., Lim, W., Rafique, N., & Thottethodi, M. (2005). Near-optimal worst-case throughput routing for two-dimensional mesh networks. ACM SIGARCH Computer Architecture News, IEEE Computer Society 33(2), 432–443. doi:10.1145/1080695.1070006
   Google Scholar
• Silva Junior, L., Nedjah, N., & Mourelle, L. (2012). Static packet routing in NoC platform using ACO-based algorithms. In H. Yin, J. A. F. Costa, & G. Barreto (Eds.), Intelligent data engineering and automated learning - IDEAL 2012. Lecture notes in computer science (Vol. 7435, pp. 84–91). Berlin: Springer.
   Google Scholar
• Silva Junior, L., Nedjah, N., & Mourelle, L. (2013). Routing for applications in NoC using ACO-based algorithms. Applied Soft Computing, 13(5), 2224–2231. doi:10.1016/j.asoc.2013.01.009
   Web of Science ®Google Scholar
• Silva Junior, L., Nedjah, N., Mourelle, L., & Pessanha, F. (2012). ACO-based static routing for network-on-chips. In B. Murgante, O. Gervasi, S. Misra, N. Nedjah, A. M. A. C. Rocha, D. Taniar, & B. O. Apduhan (Eds.), Computational science and its applications ICCSA - 2012. Lecture notes in computer science (Vol. 7333, pp. 113–124). Berlin: Springer.
   Google Scholar
• Silva, M., Nedjah, N., & Mourelle, L. (2010). Power-aware multi-objective evolutionary optimisation for application mapping on network-on-chip platforms. International Journal of Electronics, 97(10), 1163–1179. doi:10.1080/00207217.2010.512105
   Web of Science ®Google Scholar
• Sullivan, H., & Bashkow, T. (1977). A large scale, homogeneous, fully distributed parallel machine, I. ACM SIGARCH Computer Architecture News, ACM 5(7), 105–117. doi:10.1145/633615.810659
   Google Scholar
• Valiant, L. G., & Brebner, G. J. (1981). Universal schemes for parallel communication. In Proceedings of the thirteenth annual ACM symposium on theory of computing (STOC ′81) (pp. 263–277). New York, NY: ACM. doi:10.1145/800076.802479
   Google Scholar
• Zeferino, C. A., & Susin, A. A. (2003, September 8–11). Socin: A parametric and scalable network-on-chip. In Proceedings of 16th symposium on integrated circuits and systems design, 2003. SBCCI 2003 (pp. 169–174). IEEE. doi:10.1109/SBCCI.2003.1232824
   Google Scholar
• Zhao, X., & GuA, M. (2013). A novel energy-aware multi-task dynamic mapping heuristic of NoC-based MPSoCs. International Journal of Electronics, 100(5), 603–615. doi:10.1080/00207217.2012.713179
   Web of Science ®Google Scholar