Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating

References

• Agarwal, N., Krishna, T., Peh, L.-S., & Jha, N. K. (2009, April). GARNET: A detailed on-chip network model inside a full-system simulator. In Proceedings of the 2009 IEEE international symposium on performance analysis of systems and software (pp. 33–42). Boston, MA: IEEE.
   Google Scholar
• Casu, M. R., Yadav, M. K., & Zamboni, M. (2013). Power-gating technique for network-on-chip buffers. Electronics Letters, 49(23), 1438–1440. doi:10.1049/el.2013.3225
   Web of Science ®Google Scholar
• Chen, L., & Pinkston, T. M. (2012, December). NoRD: Node-router decoupling for effective power-gating of on-chip routers. In Proceedings of the 45th annual IEEE/ACM international symposium on microarchitecture (pp. 270–281). Vancouver, BC: IEEE.
   Google Scholar
• Chen, L., Zhao, L., Wang, R., & Pinkston, T. M. (2014, February). MP3: Minimizing performance penalty for power-gating of clos network-on-chip. In Proceedings of the IEEE 20th international symposium on high performance computer architecture (pp. 296–307). Orlando, FL: IEEE.
   Google Scholar
• Dally, W. J., & Towles, B. (2004). Principles and practices of interconnection networks. San Francisco, CA: Morgan Kaufmann Publishers.
   Google Scholar
• Das, R., Narayanasamy, S., Satpathy, S. K., & Dreslinski, R. G. (2013, June). Catnap: Energy proportional multiple network-on-chip. In Proceedings of the 40th annual international symposium on computer architecture (pp. 320–331). Tel-Aviv: ACM.
   Google Scholar
• Fallin, C., Craik, C., & Mutlu, O. (2011, February). CHIPPER: A low-complexity bufferless deflection router. In Proceedings of the IEEE 17th international symposium on high performance computer architecture (pp. 144–155). San Antonio, TX: IEEE.
   Google Scholar
• Feng, C., Lu, Z., Jantsch, A., & Zhang, M. (2012). A 1-cycle 1.25GHz bufferless router for 3D network-on-chip. IEICE Transactions on Information and Systems, E95-D(5), 1519–1522. doi:10.1587/transinf.E95.D.1519
   Web of Science ®Google Scholar
• Hayenga, M., Jerger, N. E., & Lipasti, M. (2009, December). SCARAB: A single cycle adaptive routing and bufferless network. In Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture (pp. 244–254). New York, NY: ACM.
   Google Scholar
• Hoskote, Y., Vangal, S., Singh, A., Borkar, N., & Borkar, S. (2007). A 5-GHz mesh interconnect for a teraflops processor. Micro, IEEE, 27(5), 51–61. doi:10.1109/MM.2007.4378783
   Web of Science ®Google Scholar
• Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., & Bose, P. (2004, August). Microarchitectural techniques for power gating of execution units. In Proceedings of the 2004 international symposium on low power electronics and design (pp. 32–37). Newport Beach, CA: ACM.
   Google Scholar
• Jain, L., Al-Hashimi, B., Gaur, M., Laxmi, V., & Narayanan, A. (2007). NIRGAM: A simulator for NoC interconnect routing and application modeling. In Proceedings of the conference on design, automation and test in Europe (DATE’07) (pp. 16–20). Nice Acropolis: IEEE.
   Google Scholar
• Jan, Y., & Jóźwiak, L. (2012a). Communication and memory architecture design of application-specific high-end multiprocessors. VLSI Design, 2012, 1–20. doi:10.1155/2012/794753
   Google Scholar
• Jan, Y., & Jóźwiak, L. (2012b). Scalable communication architectures for massively parallel hardware multi-processors. Journal of Parallel and Distributed Computing, 72(11), 1450–1463. doi:10.1016/j.jpdc.2012.01.017
   Web of Science ®Google Scholar
• Joshi, A., & Mutyam, M. (2011, May). Prevention flow-control for low latency torus networks-on-chip. In Proceedings of the 5th ACM/IEEE international symposium on networks-on-chip (pp. 41–48). Pittsburgh, PA: ACM.
   Google Scholar
• Kahng, A. B., Li, B., Peh, L.-S., & Samadi, K. (2009, April). ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the conference on design, automation and test in Europe (DATE’09) (pp. 423–428). Nice: IEEE.
   Google Scholar
• Kim, G., Kim, J., & Yoo, S. (2011, June). FlexiBuffer: Reducing leakage power in on-chip network routers. In Proceedings of the 48th design automation conference (DAC’11) (pp. 936–941). San Diego, CA: ACM.
   Google Scholar
• Kim, J. (2009, December). Low-cost router microarchitecture for on-chip networks. In Proceedings of the 42nd annual IEEE/ACM international symposium on microarchitecture (pp. 255–266). New York, NY: ACM.
   Google Scholar
• Kim, J., & Kim, H. (2009, December). Router microarchitecture and scalability of ring topology in on-chip networks. In Proceedings of the 2nd international workshop on network on chip architectures (pp. 5–10). New York, NY: ACM.
   Google Scholar
• Kim, J. S., Taylor, M. B., Miller, J., & Wentzlaff, D. (2003, August). Energy characterization of a tiled architecture processor with on-chip networks. In Proceedings of the 2003 international symposium on low power electronics and design (pp. 424–427). Seoul: ACM.
   Google Scholar
• Kumar, A., Kundu, P., Singhx, A., Peh, L.-S., & Jha, N. (2007, October). A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. In Proceedings of the IEEE 25th international conference on computer design (ICCD’07) (pp. 63–70). Lake Tahoe: IEEE.
   Google Scholar
• Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H., & Amano, H. (2011). Performance, area and power evaluations of ultrafine-grained run-time power-gating routers for CMPs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(4), 520–533. doi:10.1109/TCAD.2011.2110470
   Web of Science ®Google Scholar
• Mische, J., & Ungerer, T. (2012, December). Low power flitwise routing in an unidirectional torus with minimal buffering. In Proceedings of the fifth international workshop on network on chip architectures (pp. 63–68). Vancouver, BC: ACM.
   Google Scholar
• Rathod, N., Balachandran, S., & Gala, N. (2014, January). CAERUS: An effective arbitration and ejection policy for routing in an unidirectional torus. In Proceedings of the 8th international workshop on interconnection network architecture: On-chip, multi-chip (pp. 1–4). Vienna: ACM.
   Google Scholar
• Samih, A., Wang, R., Krishna, A., Maciocco, C., Tai, C., & Solihin, Y. (2013, February). Energy-efficient interconnect via router parking. In Proceedings of the IEEE 19th international symposium on high performance computer architecture (pp. 508–519). Shenzhen: IEEE.
   Google Scholar
• Shin, M., & Kim, J. (2011, October). Leveraging torus topology with deadlock recovery for cost-efficient on-chip network. In Proceedings of the IEEE 29th international conference on computer design (ICCD’11) (pp. 25–30). Amherst, MA: IEEE.
   Google Scholar
• Wang, H., Peh, L.-S., & Malik, S. (2003, December). Power-driven design of router microarchitectures in on-chip networks. In Proceedings of the 36th annual IEEE/ACM international symposium on microarchitecture (pp. 105–116). San Diego, CA: IEEE.
   Google Scholar
• Woo, S. C., Ohara, M., Torrie, E., Singh, J. P., & Gupta, A. (1995). The SPLASH-2 programs: Characterization and methodological considerations. In ACM SIGARCH computer architecture news (Vol. 23, pp. 24–36). ACM. doi:10.1145/225830.223990
   Google Scholar
• Zhao, B., Zhang, Y., & Yang, J. (2013, April). A speculative arbiter design to enable high-frequency many-VC router in NoCs. In Proceedings of the 7th IEEE/ACM international symposium on networks-on-chip (pp. 1–8). Tempe, AZ: IEEE.
   Google Scholar