182
Views
3
CrossRef citations to date
0
Altmetric
Original Articles

Design and simulation of high-performance lateral bipolar junction transistor on partial buried oxide

, , , &
Pages 111-125 | Received 31 May 2014, Accepted 15 May 2016, Published online: 25 Jun 2016

References

  • Alam, M. S., Lim, T. C., & Armstrong, G. A. (2006). Analog performance of double gate SOI transistors. International Journal of Electronics, 93(1), 1–18. doi:10.1080/00207210500296625
  • Awadallah, R., & Yuan, J. S. (1999). A new structure design of a silicon-on-insulator MOSFET reducing the self-heating effect. International Journal of Electronics, 86(6), 707–712. doi:10.1080/002072199133166
  • Burghartz, J. N., Cressler, J. D., Warnock, J., McIntosh, R. C., Jenkins, K. A., Sun, J. Y. C., … Danner, D. D. (1992). Partial SOI isolation structures for reduced bipolar transistors parasitics. IEEE Transactions on Electron Devices, 13(8), 424–426. doi:10.1109/55.192779
  • Cai, J., & Ning, T. H. (2004). Bipolar transistor on thin SOI: Concept, status and prospect. In Proc. of IEEE Int. Conf. on Solid State and IC Technology (vol. 3, pp. 2102–2107).
  • Chang, O. W., Kim, S. H., Kim, D.-W., Park, D., & Kim, K. (2010). Hybrid integration of ultrathin-body partially insulated MOSFETs and a bulk MOSFET for better IC performance: A multiple-VTH technology using partial SOI structure. IEEE Electron Device Letters, 31(1), 59–61. doi:10.1109/LED.2009.2034878
  • Chi-Man, N., Nguyen, C. T., Kuehne, S. C., & Wong, S. S. (1996). Evidence of reduced maximum E-field in quasi-SOI MOSFET. IEEE Transactions on Electron Devices, 43(12), 2308–2310. doi:10.1109/16.544428
  • Cohen, G. M., & Sadana, D. K. (2001). A patterned SOI by masked anneal for system- on- chip applications. U.S. Patent, No. 6 300 218.
  • Cole, B., & Parke, D. S. (2003). A method to overcome self-heating effects in SO1 MOSFETs. Journal of Nanjing Normal University, 3, 4.
  • Colinge, J. P. (1997). Silicon-on-insulator technology: Materials to VLSI. Taiwan: Springer.
  • Dong, Y., Chen, J., Wang, X., Chen, M., & Wang, X. (2004). Optimized implant dose and energy to fabricate high-quality patterned SIMOX SOI materials. Solid State Communications, 130(3–4), 275–279. doi:10.1016/j.ssc.2004.01.027
  • Dong, Y., Chen, M., Chen, J., Wang, X., Wang, X., He, P., … Li, Z. (2004). Patterned buried oxide layers under a single MOSFET to improve the device performance. Semiconductor Science and Technology, 19, L25–L28. doi:10.1088/0268-1242/19/3/L05
  • Duan, B., Zhang, B., & Li, Z. A. (2005). A new partial SOI power device structure with P-type buried layer. Solid State Electronics, 49(12), 1965–1968. doi:10.1016/j.sse.2005.09.012
  • Harame, D. L., Ahlgren, D. C., Coolbaugh, D. D., Dunn, J. S., Freeman, G. G., Gillis, J. D., … Zampardi, P. J. (2001). Current status and future trends of SiGe BiCMOS technology. IEEE Transactions Electronic Devices, 48, 2575–2594. doi:10.1109/16.960385
  • Hardikar, S., De Souza, M. M., Xu, Y. Z., Pease, T. J. T., & Narayan, E. M. S. (2004). A novel double RESURF LDMOS for HVIC’s. Journal of Microelectronics, 35, 305–310. doi:10.1016/S0026-2692(03)00190-3
  • Hu, S., Zhangb, B., & Li, Z. (2011). A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices. International Journal of Electronics, 98(7), 973–980. doi:10.1080/00207217.2011.576598
  • Kim, I. H. (2001). Effects of emitter structure variation on the RF characteristics of AlGaAs HBTs. Materials Letters, 49(6), 219–223. doi:10.1016/S0167-577X(00)00373-6
  • Ladd, G. O., & Feucht, D. L. (1970). Performance potential of high-frequency heterojunction transistors. IEEE Transactions on Electron Devices, 17(5), 413–420. doi:10.1109/T-ED.1970.16998
  • Lim, H. T., Udrea, F., Garner, D., Sheng, K., & Milne, W. (1999). Partial SOI LDMOSFETs for high side switching. Proceedings of IEEE International Semiconductor Conference, 1, 149–152.
  • Litwin, A., & Arnborg, T. (1993). Extremely compact CMOS compatible bipolar siliconon- insulator transistor for mixed high voltage and high density integrated circuit applications. In Proceedings of ESSDERC Š93.
  • Loan, S. A., Bashir, F., Akhoon, M. S., & Alamoud, A. R. M. (2016). Design and simulation of oxide and doping engineered lateral bipolar junction transistors for high power applications. Superlattices and Microstructures, 89, 120–135.
  • Loan, S. A., Qureshi, S., & Iyer, S. S. K. (2009a). A novel high breakdown voltage lateral bipolar transistor on SOI with multizone doping and multistep oxide. Semiconductor Science and Technology, 24(2), 025017. doi:10.1088/0268-1242/24/2/025017
  • Loan, S. A., Qureshi, S., & Iyer, S. S. K. (2009b). A high performance lateral bipolar transistor on SELBOX. In Proceedings of IEEE ISDRS. USA.
  • Loan, S. A., Qureshi, S., & Iyer, S. S. K. (2011). Lateral bipolar transistor on partial SOI: A 2D simulation study. In Proceedings of IEEE SIECPC (pp. 1–4).
  • Lu, Q., Ratnam, P., & Salama, C. A. (1992). Novel high voltage silicon-on-insulator MOSFETs. Solid State Electronics, 35(12), 1745–1750. doi:10.1016/0038-1101(92)90255-B
  • Merchant, S., Arnold, E., Baumgan, H., Mukhefjee, S., Pein, H., & Pinker, R. (1991). Realization of high breakdown voltage (>700 V) in thin SO1 devices. Proceedings of the 3rd International Symposium on Power Semiconductor Devices and ICs, 4, 31–35.
  • Nagano, H., Sato, T., Miyano, K., Yamada, T., & Mizushima, I. (2003). SOI/Bulk hybrid wafer fabrication process using selective epitaxial growth (SEG) technique for high end SoC applications. Japanese Journal of Applied Physics, 42, 1882–1886. doi:10.1143/JJAP.42.1882
  • Ni, H., Yamada, T., Inoh, K., Shino, T., Kawanaka, S., Yoshimi, M., & Katsumata, Y. (2000). A novel lateral bipolar transistor with 67 GHz f/sub max/ on thin-film SOI for RF analog applications. IEEE Transactions on Electron Devices, 47(7), 1536–1541. doi:10.1109/16.848304
  • Ning, T. H. (2002). Why BiCMOS and SOI BiCMOS. IBM Journal of Research and Development, 46(2–3), 181–186. doi:10.1147/rd.462.0181
  • Park, J. M., Grasser, T., Kosina, H., & Selberherr, S. (2003). A numerical study of partial-SOI LDMOSFETs. Solid State Electronics, 47(2), 275–281. doi:10.1016/S0038-1101(02)00207-1
  • Parke, S. A., Hu, C., & Ko, P. K. (1993). A high-performance lateral bipolar transistor fabricated on SIMOX. IEEE Electron Device Letters, 14(1), 33–35. doi:10.1109/55.215091
  • Qing, H., Li, Z., Zhang, B., Chen, W., Huang, X., & Feng, Y. (2015). A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications. International Journal of Electronics, 102(5), 755–764. doi:10.1080/00207217.2014.938254
  • Quyang, J., Cai, T., Ning, T., Oldiges, P., & Johnson, J. B. (2002). A simulation study on thin SOI bipolar transistors with fully or partially depleted collector. In Proceedings of BCTM (pp. 28–31).
  • Ratnam, P. (1989). Novel silicon-on-insulator MOSFET for high voltage integrated circuits. Electronics Letters, 25(8), 536–537. doi:10.1049/el:19890367
  • Roy, S. D., & Kumar, M. J. (2005). Realizing high voltage thin film lateral bipolar transistors on SOI with a collector tub. Microelectronics International, 22(1), 3–9. doi:10.1108/13565360510575486
  • Sun, I. H. M., Ng, W. T., Kanekiyo, K., Kobayashi, T., Mochizuki, H., Toita, M., … Takasuka, K. (2005). Lateral high speed bipolar transistors on SOI for RF SoC applications. IEEE Transactions on Electron Devices, 52(7), 1376–1383. doi:10.1109/TED.2005.850676
  • Sunderland, D., & Dapkus, P. D. (1987). Optimizing N-P-N and P-N-P heterojunction bipolar transistors for speed. IEEE Transactions on Electron Devices, 34(2), 367–377. doi:10.1109/T-ED.1987.22932
  • Tadikonda, R., Hardikar, S., & Narayanan, E. M. S. (2004). Realizing high breakdown voltages (> 600 V) in partial SOI technology. Solid State Electronics, 48(9), 1655–1660. doi:10.1016/j.sse.2004.04.005
  • TMA MEDICI 4.2. (2006). Palo Alto, CA: Technology Modeling Associates.
  • Washio, K. (2003). SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems. IEEE Transactions Electronic Devices, 50, 656–668. doi:10.1109/TED.2003.810484

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.