110
Views
6
CrossRef citations to date
0
Altmetric
Original Articles

Variation aware intuitive clock gating to mitigate on-chip power supply noise

ORCID Icon & ORCID Icon
Pages 1487-1500 | Received 15 Oct 2017, Accepted 25 Mar 2018, Published online: 11 Apr 2018

References

  • Bhattacharjee, P., & Majumder, A. (2016, December). LECTOR based gated clock approach to design low power FSM for serial adder. In Nanoelectronic and Information Systems (iNIS), 2016 IEEE International Symposium on (pp. 250–254). IEEE.
  • Bhattacharjee, P., Majumder, A., & Das, T. D. (2016, October). A 90 nm leakage control transistor based clock gating for low power flip flop applications. In Circuits and Systems (MWSCAS), 2016 IEEE 59th International Midwest Symposium on (pp. 1–4). IEEE.
  • Bhattacharjee, P., Majumder, A., & Nath, B. (2017). A 23.52 μW/0.7 V multi-stage flip-flop architecture steered by a LECTOR-based gated clock. IEIE Transactions on Smart Processing & Computing, 6(3), 220–227.
  • Bhattacharyya, B. K., & Baral, D. (2013). Method to simulate rise time of current drawn by a microprocessor. IEEE Transactions on Components. Packaging and Manufacturing Technology, 3(10), 1731–1736.
  • Bhowmik, S., Deb, D., Pradhan, S. N., & Bhattacharyya, B. K. (2016). Reduction of noise using continuously changing variable clock and clock gating for IC CHIPS. IEEE transactions on components. Packaging and Manufacturing Technology, 6(6), 886–896.
  • Bhowmik, S., Pradhan, S. N., & Bhattacharyya, B. K. (2017). Clock jitter reduction and flat frequency generation in PLL using autogenerated control feedback. IEEE Transactions on Components, Packaging and Manufacturing Technology, 7(11), 1832–1841.
  • Branson, C. N. (1989). U.S. Patent No. 4,819,164. Washington, DC: U.S. Patent and Trademark Office.
  • Chandrakasan, A. P., & Brodersen, R. W. (1995). Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE, 83(4), 498–523.
  • Foundry Design Kits (FDK). (n.d.). Taiwan: United Microelectronics Corporation. Retrieved from http://www.europractice-ic.com/nda_UMC.php
  • GPDK090, (n.d.). Bangalore: University Team of Cadence Design Systems. Retrieved from https://support.cadence.com/
  • Gray, P. R., Hurst, P., Meyer, R. G., & Lewis, S. (2001). Analysis and design of analog integrated circuits. Hoboken, NJ: Wiley.
  • Hanchate, N., & Ranganathan, N. (2004). LECTOR: A technique for leakage reduction in CMOS circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2), 196–205.
  • Imani, M., Jafari, M., Ebrahimi, B., & Rosing, T. S. (2015). Ultra-low power FinFET based SRAM cell employing sharing current concept. Microelectronics Reliability. Amsterdam: Elsevier.
  • Intel, Pinned Packaging. (1999, April 15). Pinned packaging: An overview of Plastic Pin Grid Array Package technology, and its physical structure, electric modeling and performance. In Intel Packaging Databook (Chapter 13; pp. 1–26). Mount Prospect, IL: Intel Corporation.
  • Jafari, M., Imani, M., & Fathipour, M. (2015). Analysis of power gating in different hierarchical levels of 2MB cache, considering variation. International Journal of Electronics, 102(9), 1594–1608.
  • Jakushokas, R., Popovich, M., Mezhiba, A. V., Köse, S., & Friedman, E. G. (2010). Power distribution networks with on-chip decoupling capacitors. Berlin: Springer Science & Business Media.
  • Karim, T. (2012). On-Chip power supply noise: Scaling, suppression and detection. Waterloo, ON: University of Waterloo.
  • Kathuria, J., Ayoubkhan, M., & Noor, A. (2011). A review of clock gating techniques. MIT International Journal of Electronics and Communication Engineering, 1(2), 106–114.
  • Khatri, D., Narang, V., Ho, M. Y., Pandey, K., & Yu, R. (2016, July). Simulation assisted uncovering and understanding of complex failures in 28nm microprocessor devices. In 2016 IEEE 23rd International Symposium on the physical and failure analysis of integrated circuits (IPFA) (pp. 64–68). Singapore: IEEE.
  • Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M., & Mitsuhashi, T. (1998, February). A clock-gating method for low-power LSI design. In Design Automation Conference 1998. Proceedings of the ASP-DAC’98. Asia and South Pacific (pp. 307–312). Yokohama, Japan: IEEE.
  • Laskar, N., Debnath, S., Majumder, A., & Bhattacharyya, B. K. (2018). A new current profile determination methodology incorporating gating logic to minimize the noise of CPU chip by 40%. Journal of Circuits, Systems and Computers, 27(03), 1850049.
  • Majumder, A. (2017). Gated clock tree circuit to reduce the noise in silicon chip. Journal of Low Power Electronics, 13(4), 576–579. American Scientific Publishers.
  • Roy, K., & Prasad, S. C. (2009). Low-power CMOS VLSI circuit design. Hoboken, NJ: John Wiley & Sons.
  • Salman, E. (2009). Switching noise and timing and characteristics in nanoscale integrated circuits. University of Rochester, New York, NY. ©Proquest 3357070.
  • Shepard, K. L., & Narayanan, V. (1997, January). Noise in deep submicron digital design. In Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design (pp. 524–531). San Jose, CA: IEEE Computer Society.
  • Sridhara, K., Biradar, G. S., & Yanamshetti, R. (2016, April). Subthreshold leakage power reduction in VLSI circuits: A survey. In 2016 International Conference on communication and signal processing (ICCSP) (pp. 1120–1124). Melmaruvathur: IEEE.
  • Strollo, A. G., Napoli, E., & De Caro, D. (2000, August). New clock-gating techniques for low-power flip-flops. In Proceedings of the 2000 international symposium on Low power electronics and design (pp. 114–119). ACM.
  • Strollo, A. G. M., Napoli, E., & De Caro, D. (2001). Low-power flip-flops with reliable clock gating. Microelectronics Journal, 32(1), 21–28.
  • Tierno, J., Rylyakov, A., Friedman, D., Chen, A., Ciesla, A., Diemoz, T., … Rao, G. (2010, June). A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor. In 2010 IEEE Symposium on VLSI circuits (VLSIC) (pp. 85–86). Honolulu, HI: IEEE.
  • Vittal, A., Ha, H., Brewer, F., & Marek-Sadowska, M. (1997, January). Clock skew optimization for ground bounce control. In Proceedings of the 1996 IEEE/ACM International Conference on computer-aided design (pp. 395–399). San Jose, CA: IEEE Computer Society.

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.