34
Views
0
CrossRef citations to date
0
Altmetric
Research Article

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ORCID Icon &
Received 27 Jan 2023, Accepted 16 Sep 2023, Published online: 20 Oct 2023

References

  • Allred, D. J., Yoo, H., Krishnan, V., Huang, W., & Anderson, D. V. (2005). LMS adaptive filters using distributed arithmetic for high throughput. IEEE Transactions on Circuits and Systems, 52(7), 1327–1337. https://doi.org/10.1109/TCSI.2005.851731
  • Anil, R., Sampath, P. P. V. A., & Kumar, P. S. (2022, December). Area efficient VLSI design for image processing using the modified CORDIC algorithm. Proceedings of the 2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA), Bangalore, India (pp. 1–7). IEEE.
  • Bsoul, A. A. M., Wilton, S. J. E., Tsoi, K. H., and Luk, W. (2016). An FPGA architecture and CAD flow supporting dynamically controlled power gating. IEEE Transactions On Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2015.2393914
  • Chen, J., Tan, J., Chang, C.-H., & Feng, F. (2016). A New Cost-aware Sensitivity-Driven algorithm for the design of FIR filters. Proceedings of the IEEE Transactions On Circuits And Systems—I: Regular Papers. https://doi.org/10.1109/TCSI.2016.2557840
  • Giustolisi, G., Mita, R., Palumbo, G., & Scotti, G. (2022). A novel clock gating approach for the design of low-power linear feedback shift registers. IEEE Access, 10, 99702–99708. https://doi.org/10.1109/ACCESS.2022.3207151
  • Gupta, Y., Bhargava, L., & Ashish Sharma, M. S. G. (2019). Hybrid buffers based coarse-grained power gated network on chip router microarchitecture. International Journal of Electronics. https://doi.org/10.1080/00207217.2019.1644674
  • Jafari, M., Imani, M., & Fathipour, M. (2015). Analysis of power gating in different hierarchical levels of 2MB cache, considering variation. International Journal of Electronics, 102(9), 1594–1608. https://doi.org/10.1080/00207217.2014.984640
  • Kim, K., Das, K. K., & Chuang, C.-T. (2007). High-density data-retention power gating structure using a four-terminal double-gate device. International Journal of Electronics, 94(4), 403–412. https://doi.org/10.1080/00207210701288918
  • Kumar Meher, P. (2014, February). Sang Yoon Park,” area-delay-power efficient Fixed-point LMS adaptive filter with Low Adaptation-delay. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(2), 362–371. https://doi.org/10.1109/TVLSI.2013.2239321
  • Kumar Sharma, V., & Pattanaik, M. (2015). A reliable ground bounce noise reduction technique for nanoscale CMOS circuits. International Journal of Electronics. https://doi.org/10.1080/00207217.2014.996786
  • Kumar Verma, B., Akashe, S., & Sharm, S. (2015). Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier. International Journal of Electronics, 102(9), 1486–1501. https://doi.org/10.1080/00207217.2014.982215
  • Lee, J. G., Choi, Y., Jeon, H., Lee, J. J., & Shin, D. (2022). Fully automated hardware-driven clock-gating architecture with complete clock coverage for 4 nm Exynos Mobile SOC. IEEE Journal of Solid-State Circuits, 58(1), 90–101. https://doi.org/10.1109/JSSC.2022.3219410
  • Majumder, A., & Bhattacharjee, P. (2018). Variation aware intuitive clock gating to mitigate on-chip power supply noise. International Journal of Electronics, 105(9), 1487–1500. https://doi.org/10.1080/00207217.2018.1460873
  • Meher, P. K., & Park, S. Y. (2011). High-throughput pipelined realization of adaptive fir filter based on distributed arithmetic. Proceedings of the IEEE/IFIP 19th International Conference On VLSI And System-On-Chip, Hong Kong, China.
  • Mike Borowczak and Ranga Vemuri. (2012).S*FSM: A paradigm shift for attack resistant FSM designs and encodings. ASE International Conference on BioMedical Computing IEEE https://doi.org/10.1109/SocialInformatics.2012.104651
  • Mishra, S. M., Shekhawat, H. S., Trivedi, G., Jan, P., & Nemec, Z. (2022, April). Design and implementation of a low power area efficient Bfloat16 based CORDIC processor. Proceedings of the 2022 32nd International Conference Radioelektronika (RADIOELEKTRONIKA), Kosice, Slovakia (pp. 1–6). IEEE.
  • Mohamed Sulaiman, S., Jaison, B., & Anto Bennet, M. (2020). Design of low power 16 bit counter with programmable combinational logic and integrated clock gating using 16nm technology. International Journal of Electronics, 108(2), 163–179. https://doi.org/10.1080/00207217.2020.1793398
  • Mushtaq, U., & Sharma, V. K. (2020). Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 33(5), e2730. https://doi.org/10.1002/jnm.2730
  • Nair, H., & Chalil, A. (2022, March). FPGA implementation of area and speed efficient CORDIC algorithm. Proceedings of the 2022 6th International Conference on Computing Methodologies and Communication (ICCMC), Erode, India (pp. 512–518). IEEE.
  • Ng, K. H., Alias, N. E., Hamzah, A., Tan, M. L. P., Sheikh, U. U., & Wahab, Y. A. (2022, August). A March 5n FSM-Based memory built-in self-test (MBIST) architecture with diagnosis capabilities. Proceedings of the 2022 IEEE International Conference on Semiconductor Electronics (ICSE), Kuala Lumpur, Malaysia (pp. 69–72). IEEE.
  • Nguyen, H.-T., Nguyen, X.-T., and Pham, C.-K., (2018). An efficient Fixed-point arithmetic processor using a hybrid CORDIC algorithm. Proceedings of the IEEE, Jeju, Korea (South).
  • Satheeskumaran, S., & Sabrigiriraj, M. (2015). VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal. International Journal of Electronics, 1362–3060. ISSN: 0020-7217 (Print). https://doi.org/10.1080/00207217.2015.1082204
  • Schlarp, J., Klemen, L., Csencsics, E., & Schitter, G. (2022, July). Improving the repeatability of a color sensor by integrating an FSM for scanning-based areal measurements. Proceedings of the 2022 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM), Sapporo, Japan (pp. 502–507). IEEE.
  • Sharma, V. K. (2022). CNTFET circuit-based wide fan-in domino logic for low power applications. Journal of Circuits, Systems and Computers, 31(2), 2250036. https://doi.org/10.1142/S0218126622500360
  • Sharma, V. K., Patel, S., & Pattanaik, M. (2014). High performance process variations aware technique for sub-threshold 8T-SRAM cell. Wireless Personal Communications, 78(1), 57–68. https://doi.org/10.1007/s11277-014-1735-x
  • Sharma, V. K., & Pattanaik, M. (2013). VLSI scaling methods and low power CMOS buffer circuit. Journal of Semiconductors, 34(9), 095001. https://doi.org/10.1088/1674-4926/34/9/095001
  • Sharma, V. K., & Pattanaik, M. (2014). Techniques for low leakage nanoscale VLSI circuits: A comparative study. Journal of Circuits, Systems, and Computers, 23(5), 1450061. https://doi.org/10.1142/S0218126614500613
  • Sharma, V. K., & Pattanaik, M. (2016). Design of low leakage variability aware ONOFIC CMOS standard cell library. Journal of Circuits, Systems and Computers, 25(11), 1650134. https://doi.org/10.1142/S0218126616501346
  • Sharma, V. K., Pattanaik, M., & Raj, B. (2014). PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectronics Reliability, 54(1), 90–99. https://doi.org/10.1016/j.microrel.2013.09.018
  • Singh, K. (2023, January). Power and area efficient hybrid memristor-CMOS based 2’s complement FSM for high-performance Computing System. Proceedings of the 2023 International Conference on Artificial Intelligence and Smart Communication (AISC), Greater Noida, India (pp. 170–174). IEEE.
  • Tong, Q., & Choi, K. (2017). Activity correlation based clustering clock gating technique for Digital filters. International Journal of Electronics, 104(7), 1095–1106. https://doi.org/10.1080/00207217.2017.1285435
  • Vinh, T. Q., Thanh, T. B., & Viet, D. H. (2022, October). FPGA implementation of trigonometric function using loop-optimized radix-4 CORDIC. Proceedings of the 2022 9th NAFOSTED Conference on Information and Computer Science (NICS), Ho Chi Minh City, Vietnam (pp. 217–222). IEEE.
  • Wang, F., Tang, X., Xing, Z., & Liu, H. (2015). Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating. International Journal of Electronics, 103(8), 1332–1348. https://doi.org/10.1080/00207217.2015.1104728
  • Zheng, P., Jiang, M., Meiping, W., Li, S. (2015). The designing of the state machine for multi-frequency IIR low-pass Digital filter. Proceeding of the 2015 IEEE International Conference on Information and Automation, Lijang, China, August.
  • Zuzak, I., Budiselic, I., & Delaca, G. (2011). Finite-state machine approach for modeling and analyzing restful Systems. Journal of Web Engineering, 10(4), 353–390. https://doi.org/10.5555/2230856.2230859

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.