105
Views
2
CrossRef citations to date
0
Altmetric
Research Articles

An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder

ORCID Icon
Pages 935-951 | Received 27 Oct 2022, Accepted 02 Oct 2023, Published online: 10 Nov 2023

References

  • Akbari, O., Kamal, M., Afzali-Kusha, A., & Pedram, M. (2017). Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(4), 1352–1361. https://doi.org/10.1109/tvlsi.2016.2643003
  • Bansal, Y., & Madhu, C. (2016). A novel high-speed approach for 16 × 16 vedic multiplication with compressor adders. Computers & Electrical Engineering, 49, 39–49. https://doi.org/10.1016/j.compeleceng.2015.11.006
  • Bianchi, V., & De Munari, I. (2020). A modular vedic multiplier architecture for model-based design and deployment on FPGA platforms. Microprocessors and Microsystems, 76, 103106. https://doi.org/10.1016/j.micpro.2020.103106
  • Bogireddy, V., & Augusta Sophy, P. (2015). Radix-2 pipelined FFT processor with Gauss Complex multiplication method and vedic multiplier. International Journal of Engineering Research & Technology, V4(4). https://doi.org/10.17577/ijertv4is041395
  • Chang, Y., Cheng, Y., Lin, Y., Liao, S., Lai, C., & Wu, T. (2019). Imprecise 4‐2 compressor design used in image processing applications. IET Circuits, Devices & Systems, 13(6), 848–856. ( Portico). https://doi.org/10.1049/iet-cds.2018.5403
  • Chen, J., Hu, J., Lee, S., & Sobelman, G. E. (2015). Hardware efficient mixed radix-25/16/9 FFT for LTE Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(2), 221–229. https://doi.org/10.1109/tvlsi.2014.2304834
  • Cho, T., & Lee, H. (2013). A high-speed low-complexity modified 25 FFT processor for high rate WPAN applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(1), 187–191. https://doi.org/10.1109/tvlsi.2011.2182068
  • Chu, Y., Yen, M.-H., Hsiung, P.-A., & Chen, S.-J. (2011). A low-power 64-point pipeline FFT/IFFT processor for OFDM applications. IEEE Transactions on Consumer Electronics, 57(1), 40–45. https://doi.org/10.1109/tce.2011.5735479
  • Cortes, A., Velez, I., & Sevillano, J. F. (2009). Radix $r^{k} $ FFTs: Matricial representation and SDC/SDF pipeline implementation. IEEE Transactions on Signal Processing, 57(7), 2824–2839. https://doi.org/10.1109/tsp.2009.2016276
  • Dhanasekar, S., Bruntha, P. M., Ahmed, L. J., Valarmathi, G., Govindaraj, V., & Priya, C. (2022). An area efficient FFT processor using modified compressor adder based vedic multiplier. 2022 6th International Conference on Devices, Circuits and Systems (ICDCS). https://doi.org/10.1109/icdcs54290.2022.9780676
  • Dhanasekar*, S., Bruntha, P. M., Madhuvappan, C. A., & Sagayam, K. M. (2019). An improved area efficient 16-QAM transceiver design using vedic multiplier for wireless applications. The International Journal of Recent Technology & Engineering (IJRTE), 8(3), 4419–4425. https://doi.org/10.35940/ijrte.c5535.098319
  • Dhanasekar, S., Bruntha, P. M., Neebha, T. M., Arunkumar, N., Senathipathi, N., & Priya, C. (2021). An area effective OFDM transceiver System with multi-radix FFT/IFFT algorithm for wireless applications. 2021 7th International Conference on Advanced Computing and Communication Systems ( ICACCS). https://doi.org/10.1109/icaccs51430.2021.9441694
  • Edavoor, P. J., Raveendran, S., & Rahulkar, A. D. (2020). Approximate Multiplier Design Using Novel Dual-Stage 4:2 Compressors. Institute of Electrical and Electronics Engineers Access, 8, 48337–48351. https://doi.org/10.1109/access.2020.2978773
  • Elango, K., & Muniandi, K. (2019). VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications. Annals of Telecommunications, 75(5–6), 215–227. https://doi.org/10.1007/s12243-019-00742-6
  • Elmenyawi, A., & Tawfeek, M. (2023). Optimization of quantum cost for low energy reversible signed/unsigned multiplier using Urdhva-Tiryakbhyam Sutra. Computer Systems Science and Engineering, 46(2), 1827–1844. https://doi.org/10.32604/csse.2023.036474
  • Esposito, D., Strollo, A. G. M., Napoli, E., De Caro, D., & Petra, N. (2018). Approximate multipliers based on new approximate compressors. IEEE Transactions on Circuits & Systems I: Regular Papers, 65(12), 4169–4182. https://doi.org/10.1109/tcsi.2018.2839266
  • Ferreira, G., Paim, G., Rocha, L. M. G., Santana, G. M., Neuenfeld, R. H., Costa, E. A. C., & Bampi, S. (2021). Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors. IET Computers & Digital Techniques, 15(3), 230–240. ( Portico). https://doi.org/10.1049/cdt2.12015
  • Fonseca, M. B., da Costa, E. A. C., & Martins, J. B. S. (2012). Design of power efficient butterflies from radix-2 DIT FFT using adder compressors with a new XOR gate topology. Analog Integrated Circuits and Signal Processing, 73(3), 945–954. https://doi.org/10.1007/s10470-012-9952-2
  • Ganjikunta, G. K., & Sahoo, S. K. (2017). An area-efficient and low-power 64-point pipeline fast Fourier Transform for OFDM applications. Integration, 57, 125–131. https://doi.org/10.1016/j.vlsi.2016.12.002
  • Ganjikunta, G. K., & Sahoo, S. K. (2020). Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g. IET Computers & Digital Techniques, 14(5), 193–200. https://doi.org/10.1049/iet-cdt.2018.5260
  • Gaur, N., Kumar, P., & Mehra, A. (2021). Design and analysis of high performance and low power FFT for DSP datapath using vedic multipliers. International Journal of Electronics Letters, 10(2), 188–199. https://doi.org/10.1080/21681724.2021.1908602
  • Gaur, N., Mehra, A., & Kumar, P. (2019). FFT using power efficient vedic multiplier. International Journal of Innovative Technology and Exploring Engineering, 8(10), 603–608. https://doi.org/10.35940/ijitee.i8922.0881019
  • Guo, Y., Sun, H., Guo, L., & Kimura, S. (2018). Low-Cost Approximate Multiplier Design using Probability-Driven Inexact Compressors. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). https://doi.org/10.1109/apccas.2018.8605570
  • Ha, M., & Lee, S. (2018). Multipliers with approximate 4–2 compressors and error recovery modules. IEEE Embedded Systems Letters, 10(1), 6–9. https://doi.org/10.1109/les.2017.2746084
  • Janakiraman, N., Nirmalkumar, P., & Akram, S. M. (2014). Coarse grained ADRES based MIMO-OFDM transceiver with new radix- 2 5 pipeline FFT/IFFT processor. Circuits, Systems, and Signal Processing, 34(3), 851–873. https://doi.org/10.1007/s00034-014-9880-8
  • Kala, S., Nalesh, S., Nandy, S. K., & Narayan, R. (2014). Energy efficient, scalable, and dynamically reconfigurable FFT architecture for OFDM Systems. 2014 Fifth International Symposium on Electronic System Design. https://doi.org/10.1109/ised.2014.12
  • Kumar, A. (2021). VLSI Implementation of Vedic Multiplier. Design and Development of Efficient Energy Systems, Wiley Online Library, 13–30. https://doi.org/10.1002/9781119761785.ch2
  • Kumar, A., Jain, N., & Rawat, P. (2015). FFT utilizing modified SQRT CSLA and proposed 5: 3 and 9: 4 compressor. International Journal of Computer Applications, 128(10), 36–40. https://doi.org/10.5120/ijca2015906648
  • Marimuthu, R., Rezinold, Y. E., & Mallick, P. S. (2017). Design and analysis of multiplier using approximate 15-4 compressor. Institute of Electrical and Electronics Engineers Access, 5, 1027–1036. https://doi.org/10.1109/access.2016.2636128
  • Momeni, A., Han, J., Montuschi, P., & Lombardi, F. (2015). Design and analysis of approximate compressors for multiplication. IEEE Transactions on Computers, 64(4), 984–994. https://doi.org/10.1109/tc.2014.2308214
  • Oppenheim, A. V., & Schafer, R. W. (2015). Digital Signal processing (Ist ed.). Pearson.
  • Padma, C., Jagadamba, P., & Reddy, P. R. (2022). Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application. Instrumentation Mesure Métrologie, 21(1), 21–26. https://doi.org/10.18280/i2m.210104
  • Poomagal, C. T., Sathish Kumar, G. A., & Mehta, D. (2021). Revisiting the ECM-KEEM protocol with vedic multiplier for enhanced speed on FPGA platforms. Journal of Ambient Intelligence and Humanized Computing, 14(4), 3475–3485. https://doi.org/10.1007/s12652-021-03480-7
  • Rauf, A., Pasha, M. A., & Masud, S. (2019). Towards design and automation of a scalable split-radix FFT processor for high throughput applications. Microprocessors and Microsystems, 65, 148–157. https://doi.org/10.1016/j.micpro.2018.12.008
  • Reddy, K. M., Vasantha, M. H., Kumar, Y. N., & Dwivedi, D. (2019). Design and analysis of multiplier using approximate 4-2 compressor. AEU-International Journal of Electronics and Communications, 107, 89–97. https://doi.org/10.1016/j.aeue.2019.05.021
  • Sahu, S. R., Bhoi, B. K., & Pradhan, M. (2020). Fast signed multiplier using Vedic Nikhilam algorithm. IET Circuits, Devices & Systems, 14(8), 1160–1166. ( Portico). https://doi.org/10.1049/iet-cds.2019.0537
  • S, R., Babu, K. R., & N, C. M. (2021). FPGA implementation of 8-bit vedic multiplier for DIT-FFT application using Urdhva Tiryagbhyam Sutra. In International journal of advanced research in science, communication and technology (pp. 156–165). Internet Archive. https://doi.org/10.48175/ijarsct-775
  • Sivanandam, K., & Kumar, P. (2019). Design and performance analysis of reconfigurable modified vedic multiplier with 3-1-1-2 compressor. Microprocessors and Microsystems, 65, 97–106. https://doi.org/10.1016/j.micpro.2019.01.002
  • Suresh, N., & Sasilatha, T. (2016). Enhanced performance of fast Fourier Transform (FFT) based cardiac system with modified compressor using vedic algorithm. Asian Journal of Research in Social Sciences and Humanities, 6(10), 483. https://doi.org/10.5958/2249-7315.2016.01029.7
  • Thakare, L. P., & Deshmukh, A. Y. (2016). Area efficient Complex floating point multiplier for reconfigurable FFT/IFFT processor based on vedic algorithm. Procedia Computer Science, 79, 434–440. https://doi.org/10.1016/j.procs.2016.03.056
  • Thamizharasan, V., & Kasthuri, N. (2021). High-speed hybrid multiplier design using a hybrid adder with FPGA implementation. IETE Journal of Research, 1–9. https://doi.org/10.1080/03772063.2022.2071771
  • Verma, A., Khan, A., & Wairya, S. (2023). Design and analysis of efficient vedic multiplier for fast Computing applications. International Journal of Computing and Digital Systems, 13(1), 643–655. https://doi.org/10.12785/ijcds/130151
  • Wang, C., Yan, Y., & Fu, X. (2015). A high-throughput low-complexity Radix-24- 22- 23- FFT/IFFT processor with parallel and normal input/output order for IEEE 802.11ad Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(11), 2728–2732. https://doi.org/10.1109/tvlsi.2014.2365586
  • Yadav, J., Kumar, A., Shareef, S., Bansal, S., & Rathour, N. (2022). Comparative analysis of vedic multiplier using various adder architectures. Journal of Physics: Conference Series, 2327(1), 012022. https://doi.org/10.1088/1742-6596/2327/1/012022

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.