Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub-100 nm regime: a TCAD simulation analysis

References

• Ahn, T. J., Lim, S. K., & Yu, Y. S. (2021). Monolithic 3D inverter with interface charge: Parameter extraction and circuit simulation. Applied Sciences, 11(24), 12151 (1–12. https://doi.org/10.3390/app112412151
   Google Scholar
• Baidya, A., Lenka, T. R., & Baishya, S. (2016). Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications. Superlattices and Microstructures, 100, 14–23. https://doi.org/10.1016/j.spmi.2016.08.028
   Web of Science ®Google Scholar
• Bashir, F., Alharbi, A. G., & Loan, S. A. (2017). Electrostatically doped DSL Schottky barrier MOSFET on SOI for low power applications. IEEE Journal of the Electron Devices Society, 6, 19–25. https://doi.org/10.1109/JEDS.2017.2762902
   Web of Science ®Google Scholar
• Calhoun, B. H., Cao, Y., Li, X., Mai, K., Pileggi, L. T., Rutenbar, R. A., & Shepard, K. L. (2008). Digital circuit design challenges and opportunities in the era of nanoscale CMOS. Proceedings of the IEEE, 96(2), 343–365. https://doi.org/10.1109/JPROC.2007.911072
   Web of Science ®Google Scholar
• Jung, S. G., Jang, D., Min, S. J., Park, E., & Yu, H. Y. (2021). Performance analysis on complementary FET (CFET) relative to standard CMOS with nanosheet FET. IEEE Journal of the Electron Devices Society, 10, 78–82. https://doi.org/10.1109/JEDS.2021.3136605
   Web of Science ®Google Scholar
• Kaharudin, K., Salehuddin, F., & Zain, A. (2023). Work-function tuning on analogue properties of junction-less strained dg-mosfet. Journal of Engineering Science & Technology, 18(1), 331–346.
   Google Scholar
• Kumar, S., Chatterjee, A. K., & Pandey, R. (2021). Performance enhancement of recessed silicon channel double gate junction less field-effect-transistor using TCAD tool. Journal of Computational Electronics, 20(6), 2317–2330. https://doi.org/10.1007/s10825-021-01774-9
   Web of Science ®Google Scholar
• Lee, S., Choi, Y., Won, S. M., Son, D., Baac, H. W., & Shin, C. (2022). Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications. Semiconductor Science and Technology, 37(3), 0350(1–03509. https://doi.org/10.1088/1361-6641/ac41e6
   Web of Science ®Google Scholar
• Loan, S. A., Kumar, S., & Alamoud, A. M. (2016). A novel double gate metal source/drain Schottky MOSFET as an inverter. Superlattices and Microstructures, 91, 78–89. https://doi.org/10.1016/j.spmi.2015.12.042
   Web of Science ®Google Scholar
• Luet Ng, L., Ho Yeap, K., Wan Ching Goh, M., & Dakulagi, V. (2023). Power consumption in CMOS circuits. IntechOpen. https://doi.org/10.5772/intechopen.105717
   Google Scholar
• Mendiratta, N., & Tripathi, S. L. (2022). 18nm n-channel and p-channel dopingless asymmetrical junctionless DG-MOSFET: Low power CMOS based digital and memory applications. Silicon, 14(11), 6435–6446. https://doi.org/10.1007/s12633-021-01417-5
   Web of Science ®Google Scholar
• Mishra, V. K., & Chauhan, R. K. (2016). Performance analysis of fully depleted ultra-thin-body (FD UTB) SOI MOSFET based CMOS inverter circuit for low power digital applications. In Information Systems Design and Intelligent Applications: Proceedings of Third International Conference INDIA 2016, 2, 375–382. Springer India. https://doi.org/10.1007/978-81-322-2752-6_37
   Google Scholar
• Naik, B. V., & Sinha, A. K. (2022a, December). Nano design of a symmetrical junction non-aligned double gate FET device with improved analog figure of merit. In 2022 International Conference on Microelectronics (ICM), 213–216. https://doi.org/10.1109/ICM56065.2022.10005472
   Google Scholar
• Naik, B. V., & Sinha, A. K. (2022b, December). RF and linearity analysis of a symmetrical junction non-aligned double gate FET device. In 2022 International Conference on Microelectronics (ICM), 217–220. https://doi.org/10.1109/ICM56065.2022.10005416
   Google Scholar
• Naik, V. B., & Sinha, A. K. (2023). TCAD performance analysis of a symmetrical double gate non-aligned junction FET device with high and low dielectric gate oxide in sub-100 nm regime. International Journal of Electronics Letters, 1–12. https://doi.org/10.1080/21681724.2023.2173803
   Google Scholar
• Pop, E. (2010). Energy dissipation and transport in nanoscale devices. Nano Research, 3(3), 147–169. https://doi.org/10.1007/s12274-010-1019-z
   Web of Science ®Google Scholar
• Rabaey, J. M., Chandrakasan, A. P., & Borivoje, N. (2003). Digital integrated circuits: A design perspective (2nd ed.). Pearson Education.
   Google Scholar
• Ramesh, R. (2017). Influence of gate and channel engineering on mitigate MOSFETs-A review. Microelectronics Journal, 66, 136–154. https://doi.org/10.1016/j.mejo.2017.06.009
   Web of Science ®Google Scholar
• Ryu, M., Bien, F., & Kim, Y. (2016). Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width. AIP Advances, 6(1), 015311(1–0153116. https://doi.org/10.1063/1.4940755
   Web of Science ®Google Scholar
• Sahu, C., & Singh, J. (2014). Device and circuit performance analysis of double gate junctionless transistors at Lg = 18 nm. Journal of Engineering, 2014(3), 105–110. https://doi.org/10.1049/joe.2013.0269
   Google Scholar
• Schaller, R. R. (2004). Technological innovation in the semiconductor industry: A case study of the International technology roadmap for semiconductors (ITRS). George Mason University.
   Google Scholar
• Wang, J., Du, G., Wei, K., Zhao, K., Zeng, L., Zhang, X., & Liu, X. (2014). Mixed-mode analysis of different mode silicon nanowire transistors-based inverter. IEEE Transactions on Nanotechnology, 13(2), 362–367. https://doi.org/10.1109/TNANO.2014.2305577
   Web of Science ®Google Scholar
• You, K. Y. (2018). Introductory chapter: RF/Microwave applications. InTech Publisher-Open access. https://doi.org/10.5772/intechopen.73574
   Google Scholar