92
Views
1
CrossRef citations to date
0
Altmetric
Research Article

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ORCID Icon &
Received 20 Mar 2023, Accepted 01 Oct 2023, Published online: 15 Nov 2023

References

  • Abedi, M., & Hasani, J. Y. (2018). A fast locking phase-locked loop with low reference spur. In Electrical engineering (icee), iranian conference on, Mashhad, Iran (pp. 92–97).
  • Ali, M. K. M., & Hashemipour, O. (2019). Fast locking technique for phase locked loop based on phase error cancellation. AEU-International Journal of Electronics and Communications, 109, 99–106. https://doi.org/10.1016/j.aeue.2019.06.025
  • Baker, R. J. (2008). Cmos: Mixed-signal circuit design. John Wiley & sons.
  • Chiu, W.-H., Huang, Y.-H., & Lin, T.-H. (2010). A dynamic phase error compensation technique for fast-locking phase-locked loops. IEEE Journal of Solid-State Circuits, 45(6), 1137–1149. https://doi.org/10.1109/JSSC.2010.2046235
  • Erfani-Jazi, H. R., & Ghaderi, N. (2015). A divider-less, high speed and wide locking range phase locked loop. AEU-International Journal of Electronics and Communications, 69(4), 722–729. https://doi.org/10.1016/j.aeue.2014.12.015
  • Gao, X., Klumperink, E. A., Socci, G., Bohsali, M., & Nauta, B. (2010). Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector. IEEE Journal of Solid-State Circuits, 45(9), 1809–1821. https://doi.org/10.1109/JSSC.2010.2053094
  • Huang, Z., Jiang, B., & Luong, H. C. (2017). A 2.1-GHz third-order cascaded PLL with sub-sampling DLL and clock-skew-sampling phase detector. IEEE Transactions on Circuits & Systems I: Regular Papers, 65(7), 2118–2126. https://doi.org/10.1109/TCSI.2017.2779514
  • Kim, K., Kim, K., & Yoo, C. (2018). A fREF/5 bandwidth type-II Charge-Pump Phase-Locked Loop with Dual-Edge Phase Comparison and sampling Loop filter. IEEE Microw. Wireless Compon. Lett, 28(9), 825–827. https://doi.org/10.1109/LMWC.2018.2860282
  • Ko, H.-G., Bae, W., Jeong, G.-S., & Jeong, D.-K. (2019). Reference spur reduction techniques for a phase-locked loop. Institute of Electrical and Electronics Engineers Access, 7, 38035–38043. https://doi.org/10.1109/ACCESS.2019.2905767
  • Kong, L., & Razavi, B. (2016). A 2.4 GHz 4 mW integer-N inductorless RF synthesizer. IEEE Journal of Solid-State Circuits, 51(3), 626–635. https://doi.org/10.1109/JSSC.2015.2511157
  • Kumar, S., & Singh, Y. K. (2023). A low-phase-noise self-aligned sub-harmonically injectionlocked PLL using aperture phase detector-based DLL windowing technique. Institute of Electrical and Electronics Engineers Access, 11, 6641–6655. https://doi.org/10.1109/ACCESS.2023.3237539
  • Li, C.-Y. (2015). Fast locking adaptive PLL using dual-edge phase-frequency detector. Microelectronics Journal, 46(12), 1413–1419. https://doi.org/10.1016/j.mejo.2015.08.012
  • Li, X., Zhang, J., Zhang, Y., Wang, W., Liu, H., & Lu, C. (2018). A 5.7–6.0 GHz CMOS PLL with low phase noise and- 68 dBc reference spur. AEU-International Journal of Electronics and Communications, 85, 23–31. https://doi.org/10.1016/j.aeue.2017.12.025
  • Razavi, B. (1997). Challenges in the design of frequency synthesizers for wireless applications. In Proceedings of cicc 97-custom integrated circuits conference, Santa Clara, CA, USA (pp. 395–402).
  • Razavi, B. (2003). Phase-locking in high-performance systems: From devices to architectures. John Wiley & Sons, Inc.
  • Razavi, B. (2020). Design of cmos phase-locked loops: From circuit level to architecture level. Cambridge University Press.
  • Rezaeian, A., Ardeshir, G., & Gholami, M. (2020). A low-power and high-frequency phase frequency detector for a 3.33-GHz delay locked loop. Circuits, Systems, and Signal Processing, 39(4), 1735–1750. https://doi.org/10.1007/s00034-019-01232-9
  • Sato, H., Kato, K., Sase, T., Ikushima, I., & Kojima, S.-I. (1992). A fast pull-in PLL IC using two-mode pull-in technique. Electronics and Communications in Japan (Part II: Electronics), 75(3), 41–51. https://doi.org/10.1002/ecjb.4420750305
  • Shu, K., & Sánchez-Sinencio, E. (2006). Cmos pll synthesizers: Analysis and design (Vol. 783). Springer Science & Business Media.
  • Woo, K., Liu, Y., Nam, E., & Ham, D. (2008). Fast-lock hybrid PLL combining fractional-N and integer-n modes of differing bandwidths. IEEE Journal of Solid-State Circuits, 43(2), 379–389. https://doi.org/10.1109/JSSC.2007.914281
  • Yoo, K., Kim, C., & Yoo, C. (2018). A fREF/5 bandwidth type-II charge-pump phase-locked loop with dual-edge phase comparison and sampling loop filter. IEEE Microwave and Wireless Components Letters, 28(9), 825–827. https://doi.org/10.1109/LMWC.2018.2860282
  • Zhao, B., Lian, Y., & Yang, H. (2013). A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme. IEEE Transactions on Circuits & Systems I: Regular Papers, 60(5), 1188–1199. https://doi.org/10.1109/TCSI.2013.2249177

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.