27
Views
0
CrossRef citations to date
0
Altmetric
Research Article

Impact of process parameters variation on noise and linearity performances of GC-JL-GAA MOSFET

, , , &
Received 02 May 2023, Accepted 26 Jan 2024, Published online: 05 Feb 2024

References

  • Agrawal, A. K., Koutilya, P. N. V. R., & Jagadesh, M. K. (2015). A pseudo 2-D surface potential model of a dual material double gate junctionless field effect transistor. Journal of Computational Electronics, 14, 686–693. https://doi.org/10.1007/s10825-015-0710-4
  • Baidya, A., Lenka, T., & Baishya, S. (2021). Linear distortion analysis of 3d double gate junctionless transistor with high-k dielectrics and gate metals. Silicon, 13(9), 3113–3120. https://doi.org/10.1007/s12633-020-00669-x
  • Brederlow, R., Weber, W., Landsidel, D. S., and Thewes, R. (1999). Fluctuations of the low frequency noise of MOS transistors and their modelling in analog and RF-circuit. In International Electron Devices Meeting, Washington, DC, USA (pp. 1–5).
  • Chen, Z., Xiao, Y., Tang, M., Xiong, Y., Huang, J., Li, J., Gu, X., & Zhou, Y. (2012). Surface-potential-based drain current model for long channel junctionless double gate MOSFETs. IEEE Transactions on Electron Devices, 59(12), 3292–3298. https://doi.org/10.1109/TED.2012.2221164
  • Chen, Y., & Xu, R. (2014). Analysis of the rf and noise performance of junctionless mosfets using monte carlo simulation. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 27(5–6), 822–833. https://doi.org/10.1002/jnm.1938
  • Chiang, T. K. (2012a). A quasi-two-dimensional threshold voltage model for short-channel junctionless. IEEE Transactions on Electron Devices, 59, 2284–2289. https://doi.org/10.1109/TED.2012.2202119
  • Chiang, T. K. (2012b). A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Transactions on Electron Devices, 59(9), 2284–2289. https://doi.org/10.1109/TED.2012.2202119
  • Colinge, J. P. (2004). Multiple-gate SOI MOSFETs. Solid-State Electronics, 48(6), 897–905. https://doi.org/10.1016/j.sse.2003.12.020
  • Djeffal, F., Ghoggali, Z., Dibi, Z., & Lakhdar, N. (2009). Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot carrier induced interface charges. Microelectronics Reliability, 49(377), 381. https://doi.org/10.1016/j.microrel.2008.12.011
  • Ghosh, P., Haldar, S., Gupta, R., & Gupta, M. (2012). An investigation of linearity performance and intermodulation distortion of gme cgt mosfet for rfic design. IEEE Transactions on Electron Devices, 59(12), 3263–3268. https://doi.org/10.1109/TED.2012.2219537
  • Gupta, V., Awasthi, H., Kumar, N., Pandey A, A. K., & Gupta, A. (2022). A novel approach to model threshold voltage and subthreshold current of graded-doped junctionless-gate-all around (GD-JL-GAA) MOSFET. Silicon, 14(6), 2989–2997. https://doi.org/10.1007/s12633-021-01084-6
  • Gupta, N., & Chaujar, R. (2016). Influence of gate metal engineering on small signal and noise behaviour of silicon nanowire mosfet for low-noise amplifiers. Applied Physics A, 122(8), 1–9. https://doi.org/10.1007/s00339-016-0239-9
  • Gupta, A., Gupta, V., Pandey, A. K., & Gupta, T. K. (2022). A novel technique to investigate the impact of temperature and process parameters on electrostatic and analog/RF performance of channel modulated junction less gate-all-around (CM-JL-GAA) MOSFET. Silicon, 14, 10613–10622. https://doi.org/10.1007/s12633-022-01794-5
  • Jin, X., Liu, X., Kwon, H. I., Lee JH, J. H., & Lee, J.-H. (2013). A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure. Solid-State Electronics, 82, 77–81. https://doi.org/10.1016/j.sse.2013.02.004
  • Karanicolas, A. N. (1996). A 2.7-V 900-MHz CMOS LNA and mixer. IEEE Journal of Solid-State Circuits, 31(12), 1939. https://doi.org/10.1109/4.545816
  • Kumar, N., Awasthi, H., Purwar, V., Gupta, A., & Dubey, S. (2022). Impact of temperature variation on analog, hot-carrier injection and linearity parameters of nanotube junctionless double-gate all-around (NJL-DGAA) MOSFETs. Silicon, 14(6), 2679–2686. https://doi.org/10.1007/s12633-021-01069-5
  • Kumari, V., Modi, N., Saxena, M., & Gupta, M. (2015). Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance. IEEE Transactions on Electron Devices, 62, 2098–2105. https://doi.org/10.1109/TED.2015.2433951
  • Kumar, N., & Raman, A. (2019). Design and analog performance analysis of charge-plasma based cylindrical GAA silicon nanowire tunnel field effect transistor. Silicon, 12(11), 1–8. https://doi.org/10.1007/s12633-019-00355-7
  • Kumar, N., & Raman, A. (2020). Low voltage charge-plasma based dopingless tunnel field effect transistor: Analysis and optimization. Microsystem Technologies, 26(4), 1343–1350. https://doi.org/10.1007/s00542-019-04666-y
  • Kumar, K., Raman, A., Raj, B., Singh, S., & Kumar, N. (2020). Design and optimization of junctionless-based devices with noise reduction for ultra-high frequency applications. Applied Physics A, 126(11), 1–11. https://doi.org/10.1007/s00339-020-04092-2
  • Lee, C. W., Borne, A., Ferain, I., Afzalian, A., Ran, R., Akhavan, N. D., Razavi, P., & Colinge, J. P. (2010). High-temperature performance of silicon junctionless MOSFETs. IEEE Transactions on Electron Devices, 57(3), 620–625. https://doi.org/10.1109/TED.2009.2039093
  • Liu, T. Y., Pan, F. M., & Sheu, J. T. (2015). Characteristics of gate-all-around junction less polysilicon nanowire transistors with twin 20-nm gates. IEEE Journal on Electron Devices, 3(5), 405–409. https://doi.org/10.1109/JEDS.2015.2441736
  • M, S., Marinov, O., Deen, M. J., & Ostling, M. (2002). A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs. IEEE Transactions on Electron Devices, 49(3), 514–520. https://doi.org/10.1109/16.987124
  • Shaeffer, D. K., & Lee, T. H. (1997). A 1.5 V, 1.5 GHz CMOS low noise amplifier. IEEE Journal of Solid-State Circuits, 32(5), 745–759. https://doi.org/10.1109/4.568846
  • Su, C. J., Tsai, T. I., Lin, Z. M., Lin, H. C., Chao, T. S., & Chao, T.-S. (2011). Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channel. IEEE Electron Device Letters, 32(4), 521–523. https://doi.org/10.1109/LED.2011.2107498

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.