http://orcid.org/0000-0002-5728-0061
References
- Satoh A, Morioka S, Takano K, et al. A compact Rijndael hardware architecture with S-box optimization. International Conference on the Theory and Application of Cryptology and Information Security. Berlin: Springer; 2001.
- Kocher P, Jaffe J, Jun B, et al. Introduction to differential power analysis. J Cryptogr Eng. 2011;1(1):5–27. doi: 10.1007/s13389-011-0006-y
- Levi I, Keren O, Fish A. Data-dependent delays as a barrier against power attacks. IEEE Trans Circ Syst I Reg Pap. 2015;62(8):2069–2078. doi: 10.1109/TCSI.2015.2452371
- Kaplan Y, Wimer S. Mixing drivers in clock-tree for power supply noise reduction. IEEE Trans Circ Syst I Reg Pap. 2015;62(5):1382–1391. doi: 10.1109/TCSI.2015.2411778
- Kim J, Joo D, Kim T. An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. Proceedings of the 50th Annual Design Automation Conference; 2013.
- Wimer S. Optimal weight allocation in rooted trees. J Combinat Optim. 2016;31(3):1023–1033. doi: 10.1007/s10878-014-9807-0
- Fishburn PJ. Clock skew optimization. IEEE Trans Comp. 1990;39(7):945–951. doi: 10.1109/12.55696
- Tam S, Rusu S, Desai NU, et al. Clock generation and distribution for the first IA-64 microprocessor. IEEE J Solid-State Circ. Nov 2000;35(11):1545–1552. doi: 10.1109/4.881198
- Churcher S, Longstaff SA. Programmable delay element. U.S. Patent 5,841,296. 1998 Nov 24.
- Baker JR. CMOS: circuit design, layout, and simulation , Vol. 1. John Wiley & Sons; 2008.
- Yuan J, Piper J. Floating-point analog-to-digital converter. The 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS'99; 1999.
- Raphaeli D. Method and system for flash type analog to digital converter. U.S. Patent 8,957,801. 2015 Feb 17.
- Burkard RE, Pleschiutschnig C, Zhang J. Inverse median problems. Discrete Optim. 2004;1(1):23–39. doi: 10.1016/j.disopt.2004.03.003
- Hua LK. Application of mathematical models to wheat harvesting. Chin Math. 1962;2:539–560.
- Goldman AJ. Optimal center location in simple networks. Trans Sci. 1971;5(2):212–221. doi: 10.1287/trsc.5.2.212
- Nguyen KT, Pham VC, Hai LH, et al. A simple linear time algorithm for computing a 1-median on cactus graphs. Appl Applied Math Int J. 2017;12(1):70–77.
- Alizadeh B, Burkard RE. Combinatorial algorithms for inverse absolute and vertex 1-center location problems on trees. Networks. 2011;58(3):190–200. doi: 10.1002/net.20427
- Nguyen KT. Inverse 1-median problem on block graphs with variable vertex weights. J Optim Theory Appl. 2016;168(3):944–957. doi: 10.1007/s10957-015-0829-2
- Levi I, Fish A, Keren O. CPA secured data-dependent delay-assignment methodology. IEEE Trans Very Large Scale Integr Syst. 2017;25(2):608–620. doi: 10.1109/TVLSI.2016.2592967
- Kim J, Kim T. Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific; 2015.
- Kim J, Kim T. Adjustable delay buffer allocation under useful clock skew scheduling. IEEE Trans Comp Aided Design Integr Circ Syst. 2017;36(4):641–654.
- Ewetz R, Koh C-K. MCMM clock tree optimization based on slack redistribution using a reduced slack graph. Design Automation Conference (ASP-DAC), 2016 21st Asia and South Pacific; 2016.