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Review Articles

3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications

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References

  • N. Verma, J. Kwong, and A. P. Chandrakasan, “Nanometer MOSFET variation in minimum energy subthreshold circuits,” IEEE Trans. Electron Devices, Vol. 55, no. 1, pp. 163–74, Jan. 2008. doi: 10.1109/TED.2007.911352
  • M. Horowitz, D. Stark, and E. Alon, “Digital circuit design trends,” IEEE J. Solid-State Circuits, Vol. 43, no. 4, pp. 757–61, Apr. 2008. doi: 10.1109/JSSC.2008.917523
  • G. Gielen, W. Dehaene, P. Christie, D. Philips, E. Draxelmayr, K. M. Janssens, and T. Vucurevich. “Analog and digital circuit design in 65 nm CMOS: End of the road?,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Mar. 2005, pp. 36–42.
  • T. Skotnicki, J. A. Hutchby, T. J. King, H. S. P. Wong, and F. Boeuf, “The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance,” IEEE Circuits Devices Mag., Vol. 21, no. 1, pp. 16–26, Jan. 2005. doi: 10.1109/MCD.2005.1388765
  • International Technology Roadmap for Semiconductors (ITRS). 2010 update. Available: http://www.itrs.net
  • J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices, Vol. 53, no. 5, pp. 1048–58, May 2006. doi: 10.1109/TED.2006.871842
  • H. K. Jung and S. Dimitrijev, “Analysis of subthreshold carrier transport for ultimate DGMOSFET,” IEEE Trans. Electron Devices, Vol. 53, no. 4, pp. 685–91, Apr. 2006. doi: 10.1109/TED.2006.870282
  • A. Kranti, T. M. Chung, D. Flandre, and J. P. Raskin, “Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications,” Solid-State Electron., Vol. 48, no. 6, pp. 947–59, Jun. 2004. doi: 10.1016/j.sse.2003.12.014
  • M. A. Pavanello, J. A. Martino, E. Simoen, R. Rooyackers, N. Collaert, and C. Claeys, “Evaluation of triple-gate FinFETs with SiO2-HfO2-TiN gate stack under analog operation,” Solid-State Electron., Vol. 51, no. 2, pp. 285–91, Feb. 2007. doi: 10.1016/j.sse.2007.01.012
  • V. Kilchytska, N. Collaer, R. Rooyackers, D. Lederer, J. P. Raskin, and D. Flandre. “Perspective of FinFETs for analog applications,” in Proc. ESSDERC 2004, pp. 65–8.
  • V. Subramanian, et al., “Planar bulk MOSFETs versus FinFETs: An analog/RF perspective,” IEEE Trans. Electron Devices, Vol. 53, no. 12, pp. 3071–9, Dec. 2006. doi: 10.1109/TED.2006.885649
  • J. P. Colinge, et al., “Nanowire transistors without junctions,” Nat. Nanotechnol., Vol. 5, pp. 225–9, Mar. 2010. doi: 10.1038/nnano.2010.15
  • C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., Vol. 94, no. 5, pp. 503–11, Feb. 2009.
  • J. P. Colinge, et al. “SOI gated resistor: CMOS without junctions,” in Proc. IEEE Int. SOI Conf., 2009, pp. 1–2.
  • C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electron., Vol. 54, no. 2, pp. 97–103, Feb. 2010. doi: 10.1016/j.sse.2009.12.003
  • C. W. Lee, et al., “High-temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, Vol. 57, no. 3, pp. 620–5, Mar. 2010. doi: 10.1109/TED.2009.2039093
  • J. M. Sallese, N. Chevillon, C. Lallement, B. Iñiguez, and F. Prégaldiny, “Charge-based modeling of junctionless double-gate field-effect transistors,” IEEE Trans. Electron Devices, Vol. 58, no. 8, pp. 2628–637, Aug. 2011. doi: 10.1109/TED.2011.2156413
  • J. Wang, G. Du, K. Wei, K. Zhao, L. Zeng, X. Zhang, and X. Liu, “Mixed-mode analysis of different mode silicon nanowire transistors-based inverter,” IEEE Trans. Nanotechnol., Vol. 13, no. 2, pp. 362–67, Mar. 2014. doi: 10.1109/TNANO.2014.2305577
  • S. J. Choi, D. Moon, S. Kim, J. H. Ahn, J. S. Lee, J. Y. Kim, and Y. K. Choi, “Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate,” IEEE Electron Device Lett., Vol. 32, no. 5, pp. 602–604, May 2011. doi: 10.1109/LED.2011.2118734
  • S. T. Bartsch, M. Arp, and A. M. Ionescu, “Junctionless silicon nanowire resonator,” IEEE J. Electron Devices Soc., Vol. 2, no. 2, pp. 8–15, Mar. 2014. doi: 10.1109/JEDS.2013.2295246
  • M. S. Parihar and A. Kranti. “volume accumulated double gate junctionless MOSFETs for low power logic technology applications,” in Proc.15th ISQED, Mar. 2014, pp. 335–40.
  • N. Vinodhkumar, Y. V. Bhuvaneshwari, K. K. Nagarajan, and R. Srinivasan, “Heavy-ion irradiation study in SOI-based and bulked-based junctionless FinFETs using 3D-TCAD simulation,” Microelectron. Reliab., Vol. 55, pp. 2647–53, 2015. doi: 10.1016/j.microrel.2015.09.011
  • A. Baidya, V. Krishnan, S. Baishya, and T. R. Lenka, “Effect of thin gate dielectrics and gate materials on simulated device characteristics of 3D double gate JNT,” Superlattices Microstruct., Vol. 77, pp. 209–18, 2015. doi: 10.1016/j.spmi.2014.11.007
  • A. Baidya, T. R. Lenka, and S. Baishya. “Performance analysis and improvement of nanoscale double gate junctionless transistor based inverter using high-K gate dielectrics,” in Proc. IEEE TENCON, Nov. 2015, pp. 1–4.
  • A. Baidya, T. R. Lenka, and S. Baishya, “Mixed-mode simulation and analysis of 3D double gate junctionless transistor for circuit applications,” Superlattices Microstruct., Vol. 100, pp. 14–23, Dec. 2016. doi: 10.1016/j.spmi.2016.08.028
  • R. Zimmermann and E. Fichtner, “Low-power logic styles: CMOS versus passtransistor logic,” IEEE J. Solid-State Circuits, Vol. 32, no. 7, pp. 1079–90, Jul. 1997. doi: 10.1109/4.597298
  • A. Baidya, T. R. Lenka, and S. Baishya, “Impact of thin high-K dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor,” Mater. Sci. Semicond. Process., Vol. 71, pp. 413–20, Nov. 2017. doi: 10.1016/j.mssp.2017.08.031

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