References
- N. Kaur, M. Rattan, and S. S. Gill, “Design and optimization of novel Shaped FinFET,” Arab. J. Sci. Eng., Vol. 44, no. 4, pp. 3101–3116, 12 July 2018. doi:10.1007/s13369-018-3428-3
- K. Han, G. Qiao, Z. Deng, and Y. Zhang, “Asymmetric drain Extension dual-kk Trigate underlap FinFET Based on RF/analog circuit,” Micromachines. (Basel), Vol. 8, no. 11, pp. 330, 9 Nov 2017. doi:10.3390/mi8110330
- R. K. Baruah, and R. P. Paily, “The effect of high-k gate dielectrics on device and circuit performances of a junctionless transistor,” J. Comput. Electron., Vol. 14, no. 2, pp. 492–499, 2015. doi:10.1007/s10825-015-0670-8
- D. Gola, B. Singh, J. Singh, S. Jit, and P. K. Tiwari, “Static and quasi-static drain current modelling of tri-gate junctionless transistor with substrate bias-induced effects,” IEEE Trans. Electron Devices, Vol. 66, no. 7, July 2019. doi:10.1109/TED.2019.2915294
- N. Loubet, T. Hook, P. Montanini, C.-W. Yeung, S. Kanakasabapathy, M. Guillom, and J. Wang. “Stacked Nano-Sheet gate-all-around transistor to enable scaling beyond FinFET”, 2017 Symposium on VLSI Technology, 03 August 2017.
- R. Entner, A. Gehring, T. Grasser, and S. Selberherr. “A comparison of quantum correction models for the three-dimensional simulation of FinFET structures”, 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 13-16 May 2004.
- S. Barraud, V. Lapras, B. Previtali, M. P. Samson, J. Lacord, S. Martinie, and T. Ernst. “Performance and design considerations for gate-all-around stacked-NanoWires FETs”, 2017 IEEE International Electron Devices Meeting (IEDM), 2017.
- J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek, “Multi- Vth Strategies of 7-nm node nano-sheet FETs with limited nano-sheet spacing,” IEEE Journal of the Electron Devices Society, Vol. 6, pp. 861–865, 25 July 2018. doi:10.1109/JEDS.2018.2859799
- E.-Y. Jeong, et al., “Investigation of RC parasitics considering middle-of-the-line in Si-bulk FinFETs for Sub-14-nm node logic applications,” IEEE Trans. Electron Devices, Vol. 62, no. 10, pp. 3441–3444, October 2015.
- J.-S. Yoon, et al., “Process-induced variations of 10-nm node bulk nFinFETs considering middle-of-line parasitics,” IEEE Trans. Electron Devices, Vol. 63, no. 9, pp. 3399–3405, September 2016.
- M. Je, J. Han, H. Shin, and K. Lee, “A simple four-terminal small signal model of RF MOSFETs and its parameter extraction,” Microelectron. Reliab., Vol. 43, no. 4, pp. 601–609, 2003. doi:10.1016/S0026-2714(02)00352-9
- J.-S. Yoon, et al., “Performance and variations induced by single interface trap of nanowire FETs at 7-nm node,” IEEE Trans. Electron Devices, Vol. 64, no. 2, pp. 339–345, February 2017.
- C. D. Young, et al. “Critical discussion on (100) and (110) orientation dependent transport: nMOS Planar and FinFET”, 2011 Symposium on VLSI Technology Digest of Technical Papers, June 2011.
- F. Gamiz, et al. “Anisotropy of electron mobility in arbitrarily oriented FinFETs”, ESSDERC 2007 - 37th European Solid State Device Research Conference, 16 January 2008.
- Genius, 3-D Device Simulator, Version 1.9.3-18, Reference Manual, Cogenda Pvt. Ltd., Singapore, 2019.
- International Technology Roadmap for Semiconductors, https://en.wikipedia.org/wiki, 2018.