Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via

References

• R. R. Schaller, “Moore's law: Past, present, and future,” IEEE Spectr., Vol. 34, no. 6, pp. 52–9, Jun. 1997. DOI: 10.1109/6.591665
   Web of Science ®Google Scholar
• C. Zhang, and G. Sun. “Fabrication cost analysis for 2D, 2.5D, and 3D IC designs,” in Proceedings of IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, Jan. 31 – Feb. 2, 2012, pp. 1–4.
   Google Scholar
• B. K. Kaushik, V. R. Kumar, M. K. Majumder, and A. Alam. Through Silicon Vias: Materials, Models, Design, and Performance, 1st ed. Boca Raton: CRC Press, Nov. 2016.
   Google Scholar
• W. R. Davis, et al., “Demystifying 3D ICs: The pros and cons of going vertical,” IEEE Des. Test Comput., Vol. 22, no. 6, pp. 498–510, Nov.–Dec. 2005. DOI: 10.1109/MDT.2005.136
   Web of Science ®Google Scholar
• J. M. Chan, C. S. Tan, K. C. Lee, X. Cheng, and W. Kanert. “Observations of copper (Cu) transport in through-silicon vias (TSV) structure by electrical characterization for its reliability evaluation,” IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, Apr. 2017, pp. 4A-3.1–4A-3.6.
   Google Scholar
• S. Chandrakar, D. Gupta, and M. K. Majumder, “Role of through silicon via in 3D integration: impact on delay and power,” J. Circuits Syst. Comput., Vol. 30, no. 3, pp. 2150051-1–2150051-23, May 2020. DOI: 10.1142/S0218126621500511.
   Web of Science ®Google Scholar
• S. Hillmann, M. H. Schulze, and H. Heuer. “High-frequency eddy current techniques,” in Handbook of Advanced Non-Destructive Evaluation, N. Ida, and N. Meyendorf, Eds. Cham: Springer, May 2018.
   Google Scholar
• D. Khalil, Y. Ismail, M. Khellah, T. Karnik, and V. De. “Analytical model for the propagation delay of through silicon vias,” in 9th International Symposium on Quality Electronic Design, San Jose, CA, USA, Mar. 2008, pp. 553–6.
   Google Scholar
• C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs,” IEEE Trans. Electron Devices, Vol. 57, no. 12, pp. 3405–17, Oct. 2010. DOI: 10.1109/TED.2010.2076382
   Web of Science ®Google Scholar
• J. Kim, et al., “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 1, no. 2, pp. 181–95, Feb. 2011. DOI: 10.1109/TCPMT.2010.2101890
   Web of Science ®Google Scholar
• S. K. Lim. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. New York: Springer, Apr. 2012, pp. 537–60.
   Google Scholar
• Q. Lu, Z. Zhu, Y. Yang, R. Ding, and Y. Li, “High-frequency electrical model of through-silicon vias for 3-D integrated circuits considering eddy current and proximity effects,” IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 7, no. 12, pp. 2036–44, Dec. 2017. DOI: 10.1109/TCPMT.2017.2741340
   Web of Science ®Google Scholar
• C. Liao, Z. Zhu, Q. Lu, X. Liu, and Y. Yang, ““Wideband electromagnetic model and analysis of shielded-pair through-silicon vias,” IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 8, no. 3, pp. 473–81, Mar. 2018. DOI: 10.1109/TCPMT.2018.2794438
   Web of Science ®Google Scholar
• V. R. Kumbhare, P. P. Paltani, and M. K. Majumder. “An efficient method to reduce crosstalk for multi-layered GNR interconnects at 32 nm technology,” 2019 IEEE 19th International Conference on Nanotechnology (IEEE-NANO), July 2019, pp. 23–7.
   Google Scholar
• Y. Peng, T. Song, D. Petranovic, and S. K. Lim, “Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling,” IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., Vol. 33, no. 12, pp. 1900–13, Dec. 2014. DOI: 10.1109/TCAD.2014.2359578
   Web of Science ®Google Scholar
• V. R. Kumbhare, P. P. Paltani, and M. K. Majumder, “Analysis of top- and side-contact MLGNR interconnects: impact on crosstalk, stability, and electromigration,” J. Comput. Electron., Vol. 19, pp. 1588–1596, Jul. 2020. DOI: 10.1007/s10825-020-01558-7.
   Web of Science ®Google Scholar
• The International Roadmap for Devices and Systems. (2020) [Online] Available: https://irds.ieee.org/editions/2020.
   Google Scholar
• W. Zhao, W. Yin, and Y. Guo, “Electromagnetic compatibility-oriented study on through silicon single-walled carbon nanotube bundle via (TS-SWCNTBV) arrays,” IEEE Trans. Electromagn. Compat., Vol. 54, no. 1, pp. 149–57, Feb. 2012. DOI: 10.1109/TEMC.2011.2167336
   Web of Science ®Google Scholar
• S. Ramo, J. R. Whinnery, and T. V. Duzer. Fields and Waves in Communication Electronics. Hoboken, NJ: Wiley-India, Feb. 1994.
   Google Scholar
• A. M. Niknejad, and R. G. Meyer, “Analysis of eddy-current losses over conductive substrates with applications to monolithic inductors and transformers,” IEEE Trans. Microwave Theory Tech., Vol. 49, no. 1, pp. 166–76, Jan. 2001. DOI: 10.1109/22.900004
   Web of Science ®Google Scholar
• F. Liang, G. Wang, D. Zhao, and B. Wang, “Wideband impedance model for coaxial through-silicon vias in 3-D integration,” IEEE Trans. Electron Devices, Vol. 60, no. 8, pp. 2498–504, Aug. 2013. DOI: 10.1109/TED.2013.2268869
   Web of Science ®Google Scholar
• D. K. Cheng. Fundamentals of Engineering Electromagnetics, Reading, MA: Addison-Wesley Pub. Co., Oct. 1992.
   Google Scholar
• J. Su, F. Wang, and W. Zhang, “Capacitance expressions and electrical characterization of tapered through-silicon Vias for 3D ICs,” IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 5, no. 10, pp. 1488–96, Oct. 2015. DOI: 10.1109/TCPMT.2015.2457938
   Web of Science ®Google Scholar
• M. N. O. Sadiku. Elements of Electromagnetics, 3rd ed. New York: Oxford University Press, Jan. 2000.
   Google Scholar
• B. K. Kaushik, S. Sarkara, and R. P. Agarwala, “Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load,” Integr. VLSI J., Vol. 40, pp. 394–405, Jul. 2007. DOI: 10.1016/j.vlsi.2006.06.001
   Web of Science ®Google Scholar
• M. K. Majumder, J. Kumar, and B. K. Kaushik, “Processinduced delay variation in SWCNT, MWCNT, and mixed CNT interconnects,” IETE. J. Res., Vol. 61, pp. 533–40, Apr. 2015. DOI: 10.1080/03772063.2015.1025110
   Web of Science ®Google Scholar
• V. R. Kumbhare, P. P. Paltani, and M. K. Majumder, “Impact of interconnect spacing on crosstalk for multi-layered graphene nanoribbon,” IETE. J. Res., 1–10, Jul. 2019. DOI: 10.1080/03772063.2019.1637788.
   Web of Science ®Google Scholar
• C. Praveen Kumar, E. S. Rao, and P. C. Sekhar, “Novel approach to analyze crosstalk for a multi-line bus system at 32-nm technology,” J. Circuits Syst. Comput., Vol. 29, no. 13, pp. 2050216-1–2050216-15, Mar. 2020. DOI: 10.1142/S0218126620502163.
   Web of Science ®Google Scholar
• S. Mohapatra, S. K. Vendra, and M. Chrzanowska-Jeske. “Through silicon via-aware layout design and power estimation in Sub-45 nanometer 3D CMOS IC technologies,” 2018 IEEE 13th Nanotechnology Materials and Devices Conference (NMDC) - Portland, OR, USA, Oct. 2018, pp. 1–4.
   Google Scholar