Investigation of Step Fin (SF), Step Drain (SD) and Step Source (SS) FinFETs with Trap Effect

REFERENCES

• M. Moore. “National Technology Roadmap for Semiconductors,” 1994.
   Google Scholar
• D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H. S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE, Vol. 89, no. 3, pp. 259–288, 2001. doi:10.1109/5.915374.
   Web of Science ®Google Scholar
• T. Watanabe, K. Tatsumura, and I. Ohdomari, “International technology roadmap for semiconductors 2005 edition,” Phys. Rev. Lett., Vol. 96, no. 19, pp. 1–23, 2006. doi:10.1103/PhysRevLett.96.196102.
   Google Scholar
• G. Iannaccone, G. Fiori, S. Reggiani, and M. Pala, “Beyond CMOS,” Nanoscale C. Innov. Mater. Model. Charact., 443–470, 2013. doi:10.1002/9781118621523.ch12.
   Google Scholar
• Y. C. Yeo, T. J. King, and C. Hu, “MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations,” IEEE Trans. Electron Devices, Vol. 50, no. 4, pp. 1027–1035, 2003. doi:10.1109/TED.2003.812504.
   Web of Science ®Google Scholar
• T. Ytterdal, Y. Cheng, and T. A. Fjeldly. MOSFET Device Physics and Operation 1.1 INTRODUCTION. 2003.
   Google Scholar
• S. M. Sze, and K. N. Kwok, Physics of semiconductor devices, Wiley– Intersci, 2007. doi:10.1007/978-3-319-03002-9.
   Google Scholar
• D. A. Neamen. Semiconductor phycics and devices.
   Google Scholar
• S. Migita, et al., “Design and demonstration of very high-k (k∼50) HfO2 for ultra-scaled Si CMOS,” Dig. Tech. Pap. - Symp. VLSI Technol., 152–153, 2008. doi:10.1109/VLSIT.2008.4588599.
   Google Scholar
• T. A. Bhat, M. Mustafa, and M. R. Beigh, “Study of short channel effects in n-FinFET structure for Si, GaAs, GaSb and GaN channel materials,” J. Nano- Electron. Phys., Vol. 7, no. 3, pp. 1–5, 2015.
   Google Scholar
• C. W. Pearce, and D. S. Yaney, “Short-Channel effects in MOSFET’s,” IEEE Electron Device Lett., Vol. 6, no. 7, pp. 326–328, 1985. doi:10.1109/EDL.1985.26143.
   Web of Science ®Google Scholar
• R. R. Das, S. Maity, A. Choudhury, A. Chakraborty, C. T. Bhunia, and P. P. Sahu, “Temperature-dependent short-channel parameters of FinFETs,” J. Comput. Electron., Vol. 17, no. 3, pp. 1001–1012, 2018. doi:10.1007/s10825-018-1212-y.
   Web of Science ®Google Scholar
• B. Y. Bin Yu, et al., “FinFET scaling to 10 nm gate length,” Dig. Int. Electron Devices Meet., 251–254, 2002. doi:10.1109/IEDM.2002.1175825.
   Google Scholar
• D. Bhattacharya, and N. K. Jha, “FinFETs: from devices to architectures,” Adv. Electron., Vol. 2014, pp. 1–21, 2014. doi:10.1155/2014/365689.
   Google Scholar
• Y. Atalla, Y. Hashim, A. N. A. Ghafar, and W. A. Jabbar, “Temperature characteristics of FinFET based on channel fin width and working voltage,” Int. J. Electr. Comput. Eng., Vol. 10, no. 6, pp. 5650–5657, 2020. doi:10.11591/ijece.v10i6.pp5650-5657.
   Google Scholar
• R. R. Das, S. Maity, D. Muchahary, and C. T. Bhunia, “Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material,” Superlattices Microstruct., Vol. 103, pp. 262–269, 2017. doi:10.1016/j.spmi.2017.01.041.
   Web of Science ®Google Scholar
• H. W. Cheng, and Y. Li, “Random work function variation induced threshold voltage fluctuation in 16-nm bulk FinFET devices with high-κ-metal-gate material,” 2010 14th Int. Work. Comput. Electron. IWCE 2010, 331–334, 2010. doi:10.1109/IWCE.2010.5677948.
   Google Scholar
• K. Ko, D. Son, M. Kang, and H. Shin, “Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability,” Solid. State. Electron., Vol. 140, pp. 74–79, 2018. doi:10.1016/j.sse.2017.10.020.
   Web of Science ®Google Scholar
• M. J. Kumar, and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Trans. Electron. Devices, Vol. 51, no. 4, pp. 569–574, 2004. doi:10.1109/TED.2004.823803.
   Web of Science ®Google Scholar
• R. R. Das, A. Chowdhury, A. Chakraborty, and S. Maity, “Impact of stress effect on triple material gate step-FinFET with DC and AC analysis,” Microsyst. Technol., Vol. 26, no. 6, pp. 1813–1821, 2020. doi:10.1007/s00542-019-04727-2.
   Web of Science ®Google Scholar
• S. S. Zaman, P. Kumar, M. P. Sarma, A. Ray, and G. Trivedi, “Design and simulation of SF-FinFET and SD-FinFET and their performance in analog, RF and digital Applications. IEEE International Symposium on Nanoelectronic and Information Systems Design., Vol. 2, pp. 200–205, 2017. doi:10.1109/iNIS.2017.49.
   Google Scholar
• K. Roy Barman, and S. Baishya, “An insight to the performance of vertical super-thin body (VSTB) FET in presence of interface traps and corresponding noise and RF characteristics,” Appl. Phys. A Mater. Sci. Process, Vol. 125, no. 12, pp. 1–12, 2019. doi:10.1007/s00339-019-3165-9.
   Web of Science ®Google Scholar
• J. Talukdar, G. Rawat, K. Singh, and K. Mummaneni, “Comparative analysis of the effects of trap charges on single- and double-gate extended-source tunnel FET with δp+ SiGe pocket layer,” J. Electron. Mater., Vol. 49, no. 7, pp. 4333–4342, 2020. doi:10.1007/s11664-020-08151-5.
   Web of Science ®Google Scholar
• T. Rudenko, V. Kilchytska, N. Collaert, M. Jurczak, A. Nazarov, and D. Flandre, “Reduction of gate-to-channel tunneling current in FinFET structures,” Solid. State. Electron., Vol. 51, no. 11–12, pp. 1466–1472, 2007. doi:10.1016/j.sse.2007.09.016.
   Web of Science ®Google Scholar
• Synopsys Inc, “Sentaurus Device User Guide – v.K-2015.06,” no. June, pp. 2009, 2009.
   Google Scholar
• B. Kumar, and R. Chaujar, “Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate All around (GS-GAA) FinFET,” Silicon, Vol. 13, no. 3, pp. 919–927, 2021. doi:10.1007/s12633-020-00910-7.
   Web of Science ®Google Scholar
• S. Routray, and K. P. Pradhan, “Assessment of Analog / RF performances for 10 nm Tri-metal Gate FinFET,” 2–5, 2020.
   Google Scholar
• J. Li, “Radio-frequency integrated circuit design,” Lect. Notes Electr. Eng., Vol. 433, pp. 133–145, 2017. doi:10.1007/978-981-10-4235-5_9.
   Google Scholar
• N. Jain, and B. Raj, “Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3N4) SOI FinFET towards analog/RF design,” J. Semicond., Vol. 39, no. 12, pp. 1–7, 2018. doi:10.1088/1674-4926/39/12/124002.
   Google Scholar
• S. Manikandan, and N. B. Balamurugan, “The improved RF/stability and linearity performance of the ultrathin-body Gaussian-doped junctionless FinFET,” J. Comput. Electron., Vol. 19, no. 2, pp. 613–621, 2020. doi:10.1007/s10825-020-01472-y.
   Web of Science ®Google Scholar
• A. Sarkar, A. Kumar Das, S. De, and C. Kumar Sarkar, “Effect of gate engineering in double-gate MOSFETs for analog/RF applications,” Microelectronics. J., Vol. 43, no. 11, pp. 873–882, 2012. doi:10.1016/j.mejo.2012.06.002.
   Web of Science ®Google Scholar