A New Approximate (8; 2) Compressor for Image Processing Applications

References

• J. Xun, V. Akhlaghi, Y. Jiang, and R. K. Gupta, “Energy-efficient neural networks using approximate computation reuse,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 1223–8. doi:10.23919/DATE.2018.8342202.
   Google Scholar
• V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan, “Analysis and characterization of inherent application resilience for approximate computing,” in Proceedings of the 50th Annual Design Automation Conference, Austin, 2013. pp. 1–9. doi:10.1145/2463209.2488873.
   Google Scholar
• Z. Wang, A. C. Bovik, H. R. Sheikh, and E. P. Simoncelli, “Image quality assessment: from error visibility to structural similarity,” IEEE Trans. Image Process., Vol. 13, no. 4, pp. 600–12, April 2004.
   PubMed Web of Science ®Google Scholar
• B. Silveira, G. Paim, B. Abreu, et al., “Power-efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design,” IEEE Trans. Circuits Syst. Regul. Pap., Vol. 64, no. 12, pp. 3126–37, August 2017. doi:10.1109/TCSI.2017.2728802.
   Web of Science ®Google Scholar
• V. Gupta, D. Mohapatra, S. Phill Park, A. Raghunathan, and K. Roy, “IMPACT: IMPrecise adders for low-power approximate computing,” in IEEE/ACM International Symposium on Low Power Electronics and Design, Fukuoka, 2011, pp. 409–14, doi:10.1109/ISLPED.2011.5993675.
   Google Scholar
• J. Han, and M. Orshansky, “Approximate computing: An emerging paradigm For energy-efficient design,” in the 18th IEEE European Test Symposium (ETS), Avignon, France, 2013, pp. 1–6, doi:10.1109/ETS.2013.6569370.
   Google Scholar
• R. Amjada, R. Hafiz, M. U. Ilyas, M. S. Younis, and M. Shafique, “m-SAAC: multi-stage adaptive approximation control to select approximate computing modes for vision applications,” Microelectron. J., Vol. 91, pp. 84–91, August 2019. Doi: 10.1016/j.mejo.2019.07.010.
   Web of Science ®Google Scholar
• B. Liu, Z. Wang, S. Guo, et al., “An energy-efficient voice activity detector using deep neural networks and approximate computing,” Microelectron. J., Vol. 87, pp. 12–21, March 2019. doi:10.1016/j.mejo.2019.03.009.
   Web of Science ®Google Scholar
• P. Choudhary, L. Bhargava, V. Singh, and A. Kumar Suhag. “Approximate Computing: Evolutionary Methods for Functional Approximation of Digital Circuits,” Elsevier Materials Today Proceeding, Online access, 2022.
   Google Scholar
• D. A. Patterson, and J. L. Hennessy. Computer Organization and Design, The Hardware/Software Interface, 5th ed. kidlington, Oxford: Morgan Kaufman Publication, Elsevier, 2014, pp. 40–45.
   Google Scholar
• Y. Gong, B. Liu, W. Ge, and L. Shi, “ARA: cross-layer approximate computing framework based reconfigurable architecture for CNNs,” Microelectron. J., Vol. 87, pp. 33–44, April 2019. doi:10.1016/j.mejo.2019.03.011.
   Web of Science ®Google Scholar
• K. Manikantta Reddy, M. H. Vasantha, Y. B. Nithin Kumar, et al., “Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications,” Integr. J., Vol. 81, pp. 268–79, August 2021. doi:10.1016/j.vlsi.2021.08.001.
   Web of Science ®Google Scholar
• O. Vikas, D. Gupta, A. Bhasin, and S. Arora, “Vedic multipiers with fast carry optimizaiton,” IETE J. Res., Vol. 51, no. 4, pp. 327–31, July 2005.
   Web of Science ®Google Scholar
• T. U. S. Krishna, K. S. Riyas, Y. Premson, and R. Sakthivel, “15–4 approximate compressor based multiplier for image processing,” in 2nd International Conference on Trends in Electronics and Informatics (ICOEI), Tirunelveli, 2018, pp. 671–5, doi:10.1109/ICOEI.2018.8553734.
   Google Scholar
• R. Marimuthu, M. Pradeepkumar, D. Bansal, S. Balamurugan, and P. S. Mallick, “Design of high speed and low power 15-4 compressor,” in Proc. International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2013, pp. 533–6. doi:10.1109/iccsp.2013.6577111
   Google Scholar
• R. Marimuthu, Y. E. Rezinold, and P. S. Mallick, “Design and analysis of multiplier using approximate 15-4 compressor,” IEEE Access, Vol. 5, pp. 1027–36, 2016. doi:10.1109/ACCESS.2016.2636128.
   Web of Science ®Google Scholar
• M. Savio, M. Dominic, and T. Deepa, “Design of higher order multiplier with approximate compressor,” in 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, 2020, pp. 1–6, doi:10.1109/CONECCT50063.2020.9198611.
   Google Scholar
• A. Gorantla, “Design of approximate compressors for multiplication,” ACM J. Emerg. Technn. Comput. Sys. (JETC), Vol. 13, no. 3, pp. 1–17, April 2017.
   Web of Science ®Google Scholar
• R. Zendegani, M. Kamal, M. Bahadori, et al, “RoBA multiplier: A rounding-based approximate multiplier for high-speed yet energy-efficient digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 25, no. 2, pp. 393–400, July 2017, doi:10.1109/TVLSI.2016.2587696.
   Web of Science ®Google Scholar
• D. Baran, M. Aktan, and V. G. Oklobdzija, “Energy efficient implementation of parallel CMOS multipliers with improved compressors,” in Proc. ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), Austin, Austin, 2010, pp. 147–52. doi:10.1145/1840845.1840876.
   Google Scholar
• I. Koren. Computer arithmetic algorithms, 2nd ed. Massachusetts: A K Peters, Ltd, 2002.
   Google Scholar
• M. Taheri, A. Arasteh, S. Mohammadyan, et al., “A novel majority based imprecise 4: 2 compressor with respect to the current and future VLSI industry,” Microprocess. Microsys. J., Vol. 73, pp. 102962, December 2020. doi:10.1016/j.micpro.2019.102962.
   Web of Science ®Google Scholar
• M. Moaiyeri, F. Sabetzadeh, and S. Angizi, “An efficient majority-based compressor for approximate computing in the nano era,” Microsyst. Technol., Vol. 24, no. 3, pp. 1589–1601, 2018.
   Web of Science ®Google Scholar
• L. Dadda, “Some schemes for fast serial input multipliers,” in IEEE 6th Symposium on Computer Arithmetic (ARITH), Aarhus, 1983. doi:10.1109/ARITH.1983.6158074.
   Google Scholar
• T. V. Fontanari, L. M. G. Rocha, et al., “An efficient N-bit 8-2 adder compressor with a constant internal carry propagation delay,” in IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), San Jose, 2020, pp. 1–4, doi:10.1109/LASCAS45839.2020.9069009.
   Google Scholar
• A. Momeni, J. Han, P. Montuschi, and F. Lombardi, “Design and analysis of approximate compressors for multiplication,” IEEE Trans. Comput., Vol. 64, no. 4, pp. 984–94, Feb. 2015. doi:10.1109/TC.2014.2308214.
   Web of Science ®Google Scholar
• M. Rouholamini, O. Kavehie, A. Mirbaha, S. J. Jasbi, and K. Navi, “A New design for 7:2 compressors,” in IEEE/ACS International Conference on Computer Systems and Applications, Amman, 2017. doi:10.1109/AICCSA.2007.370924.
   Google Scholar
• J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of approximate and probabilistic adders,” IEEE Trans. Comp., Vol. 62, no. 9, pp. 1760–71, September 2013. doi:10.1109/TC.2012.146.
   Web of Science ®Google Scholar