Advanced search
Publication Cover
Materials and Manufacturing Processes Volume 26, 2011 - Issue 9
Submit an article Journal homepage
132
Views
3
CrossRef citations to date
0
Altmetric
Original Articles

Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

Chun-Jen Weng ITRI/Center for General Education, National University of Taiwan, TaiwanCorrespondence[email protected]
Pages 1104-1110 | Received 24 Aug 2010, Accepted 02 Oct 2010, Published online: 18 Aug 2011

REFERENCES

  • Li , H.Y. ; Su , Y.J. ; Tsang , C.F. ; Sohan , S.M. ; Bliznetsov , V. ; Zhang , L. Process improvement of 0.13 lm Cu/Low K dual damascene interconnection . Microelectronics Reliability 2005 , 45 , 1134 – 1143 .
  • Haruhiko , A. ; Masahiro , Y. ; Nobuo , F. Developments of plasma etching technology for fabricating semiconductor devices . Japanese Journal of Applied Physics 2008 , 47 , 1435 – 1455 .
  • Zhao , L.L. ; Shen , M.H. ; Han , Q.H. ; Zhang , H.Y. ; Chang , S.M. A study of 65 nm BEOL trench etch issues. Int. Conf. Solid State Integr . Circuits Technol. Proc. ICSICT 2008 , 1173 – 1176 .
  • Borthakur , S. ; Satyanarayana , S. ; Knorr , A. ; Kraatz , M. ; Ho , P. Reduction of the initial defect density and improvement of the reliability of Cu/low-k structures by a methylating treatment . J. Vac. Sci. Technol. B Microelectron Nanometer Struct. 2005 , 23 , 2222 – 2225 .
  • Kriz , J. ; Angelkort , C. , Czekalla , M. ; Huth , S. ; Meinhold , D. ; Pohl , A. ; Schulte , S. ; Thamm , A. ; Wallace , S ; Overview of dual damascene integration schemes in Cu BEOL integration . Microelectronic Engineering 2008 , 85 , 2128 – 2132 .
  • Wang Robin , C.J. ; Lee , C.C. ; Chen , L.D. ; Wu , K. ; Chang-Liao , K.S. A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect . Microelectronics Reliability 2006 , 46 , 1673 – 1678 .
  • Lin , M.H. ; Chang , K.P. ; Su , K.C. ; Wang , T. Effects of width scaling and layout variation on dual damascene copper interconnect electromigration . Microelectronics Reliability 2007 , 47 , 2100 – 2108 .
  • He , F. ; Tan , C.M. Circuit level interconnect reliability study using 3D circuit model . Microelectronics Reliability 2010 , 50 , 376 – 390 .
  • Yung , K.C. ; Wang , J. ; Huang , S.Q. ; Lee , C.P. ; Yue , T.M. Modeling the etching rate and uniformity of plasma-aided manufacturing using statistical experimental design . Materials and Manufacturing Processes 2006 , 21 , 899 – 906 .
  • Weng , C.J. Novel approach of semiconductor manufacturing process on copper dual damascene processes integration . Strain 2009 , 45 , 221 – 231 .
  • Weng , C.J. Nanotechnology copper interconnect processes integrations for high aspect ratio without middle etching stop layer . Materials Science in Semiconductor Processing 2010 , 13 , 56 – 63 .

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Order Reprints Request Corporate Permissions

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

Request Academic Permissions

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.

Related research

People also read lists articles that other readers of this article have read.

Recommended articles lists articles that we recommend and is powered by our AI driven recommendation engine.

Cited by lists all citing articles based on Crossref citations.
Articles with the Crossref icon will open in a new tab.