Quasi-analytical model-based performance analysis of dual material gate stack strained GAA FinFET

References

• Atlas User’s Manual. (2015). SILVACO. https://download.silvaco.com/getfile.php?file=atlas_users1.pdf&time=1541755593&key=tqCqploHjYLQ0l1gfhUum
   Google Scholar
• Banerjee, P., & Sarkar, S. K. (2017). 3-D analytical modeling of dual-material triple-gate silicon-on-nothing MOSFET. IEEE Transactions on Electron Devices, 64(2), 368–375.
   Web of Science ®Google Scholar
• Chu, J. O., Cobb, M. A., Saunders, P. A., & Shi, L. (2004). US7235812B2. Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques.
   Google Scholar
• Colinge, J. P. (2013, April). 3D transistors. International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan.
   Google Scholar
• Dinh, T. V., Kraus, R., & Jungemann, C. (2010). Investigation of the performance of strained-SiGe vertical IMOS-transistors. Solid-State Electronics, 54(9), 942–949.
   Web of Science ®Google Scholar
• Doris, B. B., He, H., Kanakasabapathy, S. K., Karve, G., Lie, F. L., & Sieg, S. A. (2017). Strained finFET device fabrication,Washington, USA (US9805991B2, U.S Patent).
   Google Scholar
• Gao, H. W., Wang, Y. H., & Chiang, T. K. (2017). A quasi-3-D scaling length model for trapezoidal FinFET and its application to subthreshold behavior analysis. IEEE Transactions on Nanotechnology, 16(2), 281–289.
   Web of Science ®Google Scholar
• Goel, E., Kumar, S., Singh, K., Singh, B., Kumar, M., & Jit, S. (2016). s2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Transactions on Electron Devices, 63(3), 966–973.
   Web of Science ®Google Scholar
• Isabelle, F., & Cynthia, A. C. (2011). Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature, 479(7373), 310–316.
   PubMed Web of Science ®Google Scholar
• Jaafar, H., Aouaj, A., Bouziane, A., & Iñiguez, B. (2018). An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET. International Journal of Electronics Letters, 1–15. doi:10.1080/21681724.2018.1540058
   Google Scholar
• Karatsori, T. A., Theodorou, C. G., Haendler, S., Planes, N., Ghibaudo, G., & Dimitriadis, C. A. (2016). Hot-carrier degradation model for nanoscale ultra-thin body ultra-thin box SOI MOSFETs suitable for circuit simulators. Microelectronic Engineering.159, 9–16.
   Web of Science ®Google Scholar
• Kim, Y. B. (2010). Challenges for nanoscale MOSFETs and emerging nanoelectronics. Transactions on Electrical and Electronic Materials, 11(3), 93–105.
   Google Scholar
• Kranti, A., Haldar, S., & Gupta, R. S. (2001). Analytical model for threshold and I-V characteristic of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectronic Engineering, 56(3–4), 241–259.
   Web of Science ®Google Scholar
• Kumari, V., Kumar, A., Sexana, M., & Gupta, M. (2018). Empirical model for nonuniformly doped symmetric double-gate junctionless transistor. IEEE Transactions on Electron Devices, 65(1), 314–321.
   Web of Science ®Google Scholar
• Larson, L. A., Williams, J. M., & Current, M. I. (2011). Ion implantation for semiconductor doping and materials modification. Reviews of Accelerator Science and Technology, 4(1), 11–40.
   Google Scholar
• Long, W., Ou, H., Kuo, J.-M., & Chin, K. K. (1999). Dual-material gate (DMG) field effect transistor. IEEE Transactions on Electron Devices, 46(5), 865–870.
   Web of Science ®Google Scholar
• McNeill, D. W., Bhattacharya, S., Wadsworth, H., Ruddell, F. H., Mitchell, S. J. N., Armstrong, B. M., & Gamble, H. S. (2008). Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates. Journal of Materials Science: Materials in Electronics, 19(2), 119–123.
   Web of Science ®Google Scholar
• Oh, S., Monroe, D., & Hergenrother, J. M. (2000). Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Device Letters, 21(9), 445–447.
   Web of Science ®Google Scholar
• Park, S. H., Liu, Y., Kharche, N., Jelodar, M. S., Klimeck, G., Lundstrom, M. S., & Luisier, M. (2012). Performance comparisons of III–V and strained-Si in planar FETs and nonplanar FinFETs at ultrashort gate length (12 nm). IEEE Transactions on Electron Devices, 59(8), 2107–2114.
   Web of Science ®Google Scholar
• Rahou, F. Z., Bouazza, A. G., & Bouazza, B. (2016). Performance improvement of Pi-gate SOI MOSFET transistor using high-k dielectric with metal gate. IETE Journal of Research, 62(3), 331–338.
   Web of Science ®Google Scholar
• Ruiz, F. J. G., Tienda-Luna, I. M., Godoy, A., Donetti, L., & Gámiz, F. (2009). Equivalent oxide thickness of trigate SOI MOSFETs with High- kappa insulators. IEEE Transactions on Electron Devices, 56(11), 2711–2719.
   Web of Science ®Google Scholar
• Saha, R., Bhowmick, B., & Baishya, S. (2018). Analytical threshold voltage and subthreshold swing model for TMG FinFET. International Journal of Electronics. doi:10.1080/00207217.2018.1545258
   Web of Science ®Google Scholar
• Semiconductor Industry Association. (2013). Emerging research devices, international technology roadmap for semiconductors.Washington, USA.
   Google Scholar
• Sharan, N., & Mahapatra, S. (2016). Compact noise modelling for common double-gate metal–Oxide–Semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetry. IET Circuits, Devices & Systems, 10(1), 62–67.
   Web of Science ®Google Scholar
• Shih, C. W., & Chin, A. (2016). New material transistor with record-high field-effect mobility among wide-band-gap semiconductors. ACS Applied Materials Interfaces, 8(30), 19187–19191.
   PubMed Web of Science ®Google Scholar
• Shora, A. T., & Khanday, F. A. (2018). 3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET. Journal of Semiconductors, 39(12), 1-6.
   Web of Science ®Google Scholar
• Stillmaker, A., & Baas, B. (2017). Scaling equations for the accurate prediction of CMOS Device Performance from 180 nm to 7 nm. Integration, 58, 74–81.
   Web of Science ®Google Scholar
• Suzuki, K., Tosaka, Y., & Sugii, T. (1996). Analytical threshold model for short channel double gate SOI MOSFET’s. IEEE Transactions on Electron Devices, 42(8), 1166–1168.
   Google Scholar
• Theng, A. L., Goh, W. L., Chan, Y. T., Tee, K. M., Chan, L., & Ng, C. M. (2007, December). Realization of Gate-All-Around (GAA) SOI MOSFET using replacement gate mask. 2007 IEEE Conference on Electron Devices and Solid-State Circuits (pp.1129–1131), Tainan, Taiwan.
   Google Scholar
• Tienda-Luna, I. M., Ruiz, F. J. G., Godoy, A., Biel, B., & Gámiz, F. (2011). Influence of orientation, geometry, and strain on electron distribution in silicon gate-all-around (GAA) MOSFETs. IEEE Transactions on Electron Devices, 58(10), 3350–3357.
   Web of Science ®Google Scholar
• Xie, Q., Lee, Q. L., Xu, J., Wann, C., Sun, J. C., & Taur, Y. (2013). Comprehensive analysis of short-channel effects in ultrathin SOI MOSFETs. IEEE Transactions Electron Devices, 60(6), 1814–1819.
   Web of Science ®Google Scholar