Design and analysis of novel QCA full adder-subtractor

References

• Abedi, D., & Jaberipur, G. (2018). Decimal full adders specially designed for quantum-dot cellular automata. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(1), 106–110.
   Web of Science ®Google Scholar
• Abedi, D., Jaberipur, G., & Sangsefidi, M. (2015). Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. IEEE Transactions on Nanotechnology, 14(3), 497–504.
   Web of Science ®Google Scholar
• Ahmad, F., Bhat, G. M., Khademolhosseini, H., Azimi, S., Angizi, S., & Navi, K. (2016). Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells. Journal of Computational Science, 16, 8–15.
   Web of Science ®Google Scholar
• Balali, M., & Rezai, A. (2018). Design of low-complexity and high-speed coplanar four-bit ripple carry adder in QCA technology. International Journal of Theoretical Physics, 57, 1948–1960.
   Web of Science ®Google Scholar
• R. Bardhan, T. Sultana and N. J. Lisa, “An efficient design of adder/subtractor circuit using quantum dot cellular automata,” 2015 18th International Conference on Computer and Information Technology (ICCIT), Dhaka, 2015, pp. 495-500.doi: https://doi.org/10.1109/ICCITechn.2015.7488121
   Google Scholar
• Barughi, Y. Z., & Heikalabad, S. R. (2017). A three-layer full adder/subtractor structure in quantum-dot cellular automata. International Journal of Theoretical Physics, 56, 2848–2858.
   Web of Science ®Google Scholar
• Cocorullo, G., Corsonello, P., Frustaci, F., & Perri, S. (2017). Design of efficient BCD adders in quantum-dot cellular automata. IEEE Transactions on Circuits and Systems II: Express Briefs, 64(5), 575–579.
   Web of Science ®Google Scholar
• Jing Huang, M. Momenzadeh, M. B. Tahoori and F. Lombardi, “Defect characterization for scaling of QCA devices,” 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings., Cannes, France, 2004, pp. 30-38.doi: 10.1109/DFTVS.2004.1347822
   Google Scholar
• Jaiswal, A., Agrawal, A., & Roy, K. (2017). Robust and cascadable nonvolatile magnetoelectric majority logic. IEEE Transactions on Electron Devices, 64(12), 5209–5216.
   Web of Science ®Google Scholar
• Kianpour, M., Nadooshan, R. S., & Navi, K. (2014). A novel design of 8-bit adder/subtractor by quantum-dot cellular automata. Journal of Computer and System Sciences, 80(7), 1404–1414.
   Web of Science ®Google Scholar
• Labrado, C., & Thapliyal, H. (2016a). Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing. Electronics Letters, 52(6), 464–466.
   Web of Science ®Google Scholar
• Labrado, C., & Thapliyal, H. (2016b). Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing. Electronics Letters, 52(19), 1618–1620.
   Web of Science ®Google Scholar
• Lent, C. S., Isaksen, B., & Lieberman, M. (2003). Molecular quantum-dot cellular automata. Journal of the American Chemical Society, 125, 1056–1063.
   PubMed Web of Science ®Google Scholar
• Li, W., Yang, Y., Yan, H., & Liu., Y. (2013). Three-input majority logic gate and multiple input logic circuit based on DNA strand displacement. Nano Letters, 13(6), 2980–2988.
   PubMed Web of Science ®Google Scholar
• Mohammadi, M., Mohammadi, M., & Gorgin, S. (2016). An efficient design of full adder in quantum-dot cellular automata technology. Microelectronics Journal, 50, 35–43.
   Web of Science ®Google Scholar
• Momenzadeh, M., Huang, J., Tahoori, M. B., & Lombardi, F. (2005). On the evaluation of scaling of QCA devices in the presence of defects at manufacturing. IEEE Transactions on Nanotechnology, 4(6), 740–743.
   Web of Science ®Google Scholar
• M. Momenzadeh, M. Ottavi and F. Lombardi, “Modeling QCA defects at molecular-level in combinational circuits,” 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), Monterey, CA, 2005, pp. 208-216.doi: https://doi.org/10.1109/DFTVS.2005.46.
   Google Scholar
• Nikonov, D. E., Bourianoff, G. I., & Ghani, T. (2011a). Proposal of a spin torque majority gate logic. IEEE Electron Device Letters, 32(8), 1128–1130.
   Web of Science ®Google Scholar
• D. E. Nikonov, G. I. Bourianoff and T. Ghani, “Nanomagnetic circuits with spin torque majority gates,” 2011 11th IEEE International Conference on Nanotechnology, Portland, OR, 2011, pp. 1384-1388. doi: https://doi.org/10.1109/NANO.2011.6144490.
   Google Scholar
• Oya, T., Asai, T., Fukui, T., & Amemiya, Y. (2003). A majority-logic device using an irreversible single-electron box. IEEE Transactions on Nanotechnology, 2(1), 15–22.
   Web of Science ®Google Scholar
• Perri, S., Corsonello, P., & Cocorullo, G. (2014). Area-delay efficient binary adders in QCA. IEEE Transactions on Very Large Scale Integration Systems, 22(5), 1174–1179.
   Google Scholar
• Pudi, V., & Sridharan, K. (2012). Low complexity design of ripple carry and brent–kung adders in QCA. IEEE Transactions on Nanotechnology, 11(1), 105–119.
   Web of Science ®Google Scholar
• V. Pudi and K. Sridharan, “Efficient QCA design of single-bit and multi-bit subtractors,” 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013), Beijing, 2013, pp. 1155-1158. doi: https://doi.org/10.1109/NANO.2013.
   Google Scholar
• M. Sangsefidi, M. Karimpour and M. Sarayloo, “Efficient Design of a Coplanar Adder/Subtractor in Quantum-Dot Cellular Automata,” 2015 IEEE European Modelling Symposium (EMS), Madrid, 2015, pp. 456-461. doi: https://doi.org/10.1109/EMS.2015.74.
   Google Scholar
• Sasamal, T. N., Singh, A. K., & Ghanekar, U. (2016). Design of non-restoring binary array divider in majority logic-based QCA. Electronics Letters, 52(24), 2001–2003.
   Web of Science ®Google Scholar
• Sasamal, T. N., Singh, A. K., & Mohan, A. (2016). An optimal design of full adder based on 5-input majority gate in coplanar quantum-dot cellular automata. Optik, 127(20), 8576–8591.
   Web of Science ®Google Scholar
• Tahoori, M. B., Huang, J., Momenzadeh, M., & Lombardi, F. (2005, December). Characterization, test, and logic synthesis of And-Or-inverter (AOI) gate design for QCA implementation’. Ieee Tcad, 24(12), 1881–1893.
   Google Scholar
• M. B. Tahoori, M. Momenzadeh, Jin Huang and F. Lombardi, “Defects and faults in quantum cellular automata at nano scale,” 22nd IEEE VLSI Test Symposium, 2004. Proceedings., Napa Valley, CA, USA, 2004, pp. 291-296. doi: https://doi.org/10.1109/VTEST.2004.1299255.
   Google Scholar
• Yang, G., Hung, W. N. N., Song, X., & Perkowski, M. (2005). Majority-based reversible logic gates. Theoretical Computer Science, 334(1–3), 259–274.
   Web of Science ®Google Scholar