49
Views
0
CrossRef citations to date
0
Altmetric
Articles

An Efficient and Optimized Converter for Fast Binary to Decimal Conversion

, ORCID Icon, &

References

  • Ahmed, S. E., Varma, S., & Srinivas, M. B. (2018). Improved designs of digit-by-digit decimal multiplier. Integration, 61, 150–159. https://doi.org/10.1016/j.vlsi.2017.12.001
  • Al-Khaleel, O., Al-qudahj, Z., Al-Khaleel, M., Papachristou, C. A., & Wolff, F. (2011). Fast and compact binary-to- BCD conversion circuits for decimal multiplication, in: Proceedings of the 2011 IEEE international conference on computer design (ICCD) (pp. 226–231).
  • Bhattacharya, J., Gupta, A., & Singh, A. (2010). A high performance binary to BCD converter for decimal multiplication, in: Proceedings of the 2010 international symposium on VLSI design automation and test, IEEE, (pp. 315–318).
  • Couleur, J. F. (1958). BIDEC-A binary-to-decimal or decimal-to-binary converter. IRE Transactions on Electronic Computers, 4(4), 313–316. https://doi.org/10.1109/TEC.1958.5222665
  • Dadda, L., & Nannarelli, A. (2008). A variant of a radix-10 combinational multiplier, in: proceedings of the 2008 IEEE International Symposium on Circuits and Systems, IEEE, (pp. 3370–3373).
  • Dadda, L. (2007). Multioperand parallel decimal adder: A mixed binary and BCD approach. IEEE Transactions on Computers, 10(10), 1320–1328. https://doi.org/10.1109/TC.2007.1067
  • Erle, M., & Schulte, M. (2003). Decimal multiplication via carry-save addition, in: Proceedings of the 2003 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, IEEE, (pp. 348–358).
  • Erle, M., Schwarz, E., & Schulte, M. (2005). Decimal multiplication with efficient partial product generation, in:Proceedings of the 2005 IEEE Symposium on Computer Arithmetic,Cape Cod, IEEE, (pp. 21–28).
  • Han, L., & Ko, S.-B. (2013). High-speed parallel decimal multiplication with redundant internal encodings. IEEE Transactions on Computers, 62(5), 956–968. https://doi.org/10.1109/TC.2012.35
  • Jaberipur, G., & Kaivani, A. (2007). Binary-coded decimal digit multipliers. IET Comput. Digit. Tech, 1(4), 377–381. https://doi.org/10.1049/iet-cdt:20060160
  • Jaberipur, G., & Kaivani, A. (2009). Improving the speed of parallel decimal multiplication. IEEE Transactions on Computers, 58(11), 1539–1552. https://doi.org/10.1109/TC.2009.110
  • James, R., Shahana, T., Jacob, K., & Sasi, S. (2008). Decimal multiplication using compact BCD multiplier, in: Proceedings of the 2008 International conference on electronic design, IEEE, (pp. 1–6).
  • Nicoud, J.-D. (1971). Iterative arrays ror radix conversion. IEEE Transactions on Computers, 100(12), 1479–1489. https://doi.org/10.1109/T-C.1971.223160
  • Rhyne, V. T. (1970). Serial binary-to-decimal and decimal-to-binary conversion. IEEE Transactions on Computers,100(9) , 80–812.   https://doi.org/10.1109/T-C.1970.223044
  • Vazquez, A., Antelo, E., & Montuschi, P. (2010). Improved design of high-performance parallel decimal multipliers. IEEE Transactions on Computers, 59(5), 679–693. https://doi.org/10.1109/TC.2009.167

Reprints and Corporate Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

To request a reprint or corporate permissions for this article, please click on the relevant link below:

Academic Permissions

Please note: Selecting permissions does not provide access to the full text of the article, please see our help page How do I view content?

Obtain permissions instantly via Rightslink by clicking on the button below:

If you are unable to obtain permissions via Rightslink, please complete and submit this Permissions form. For more information, please visit our Permissions help page.