Electrostatically Doped Schottky barrier tunnel field effect transistor

References

• ATLAS, ATLAS User Manual. (2015). Silvaco International, Santa Clara, CA.
   Google Scholar
• Baldauf, T., Heinzig, A., Trommer, J., Mikolajick, T., & Weber, W. M. (2017). Tuning the tunneling probability by mechanical stress in Schottky barrier based reconfigurable nanowire transistors. Solid-State Electronics, 128, 148–154. https://doi.org/10.1016/j.sse.2016.10.009
   Web of Science ®Google Scholar
• Boucart, K., & Ionescu, A. M. (2007). Length scaling of the double gate tunnel FET with a high-k gate dielectric. Solid-State Electronics, 51(11–12), 1500–1507. https://doi.org/10.1016/j.sse.2007.09.014
   Web of Science ®Google Scholar
• Ghosh, P., & Bhowmick, B. (2020). Effect of temperature on reliability issues of ferroelectric dopant segregated schottky barrier tunnel field effect transistor (Fe DS-SBTFET). Silicon, 12(5), 1137–1144. https://doi.org/10.1007/s12633-019-00206-5
   Web of Science ®Google Scholar
• Guin, S., Chattopadhyay, A., Karmakar, A., & Mallik, A. (2014). Impact of a pocket doping on the device performance of a Schottky tunneling field-effect transistor. IEEE Transactions on Electron Devices, 61(7), 2515–2522. doi:10.1109/TED.2014.2325068
   Web of Science ®Google Scholar
• Guo, J., & Lundstrom, M. S. (2002). A computational study of thin-body, double-gate, Schottky barrier MOSFETs. IEEE Transactions on Electron Devices, 49(11), 1897–1902. https://doi.org/10.1109/TED.2002.804696
   Web of Science ®Google Scholar
• Ionescu, A. M., & Riel, H. (2011). Tunnel field-effect transistors as energy-efficient electronic switches. Nature, 479(7373), 329–337. https://doi.org/10.1038/nature10679
   PubMed Web of Science ®Google Scholar
• Jhaveri, R., Nagavarapu, V., & Woo, J. (2009). Asymmetric Schottky tunneling source SOI MOSFET design for mixed-mode applications. IEEE Transactions on Electron Devices, 56(1), 93–99. https://doi.org/10.1109/TED.2008.2008161
   Web of Science ®Google Scholar
• Kaity, A., Singh, S., & Kondekar, P. N. (2020). Silicon-On-Nothing Electrostatically Doped Junctionless Tunnel Field Effect Transistor (SON-ED-JLTFET): A short channel effect resilient design. Silicon, 13(1), pp.9-23.  d oi.org/1 0.1007/s12633-020-00404-6
   Web of Science ®Google Scholar
• Kim, J., Jhaveri, R., Woo, J. I., & Yang, C. K. K. (2011). Circuit-level performance evaluation of Schottky tunneling transistor in mixed-signal applications. IEEE Transactions on Nanotechnology, 10(2), 291–299. https://doi.org/10.1109/TNANO.2009.2039646
   Web of Science ®Google Scholar
• Kumar, H., Singh, S., Priyadarshani, K. N., Ghosh, J., & Naugarhiya, A. (2020). Contact engineered charge plasma junctionless transistor for suppressing tunneling leakage. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 4(1), p.e2812, 2021.DOI: 1 0.1 002/jnm.2812
   Web of Science ®Google Scholar
• Kumar, M. J., & Janardhanan, S. (2013). Doping-less tunnel field effect transistor: Design and investigation. IEEE Transactions on Electron Devices, 60(10), 3285–3290. https://doi.org/10.1109/TED.2013.2276888
   Web of Science ®Google Scholar
• Kumar, P., & Bhowmick, B. (2019). Comparative analysis of hetero gate dielectric hetero structure tunnel FET and Schottky Barrier FET with n+ pocket doping for suppression of ambipolar conduction and improved RF/linearity. Journal of Nanoelectronics and Optoelectronics, 14(2), 261–271. https://doi.org/10.1166/jno.2019.2488
   Web of Science ®Google Scholar
• Li, W., & Woo, J. C. (2018). Optimization and scaling of Ge-pocket TFET. IEEE Transactions on Electron Devices, 65(12), 5289–5294. https://doi.org/10.1109/TED.2018.2874047
   Web of Science ®Google Scholar
• Rajasekharan, B., Hueting, R. J., Salm, C., van Hemert, T., Wolters, R. A., & Schmitz, J. (2010). Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Letters, 31(6), 528–530. https://doi.org/10.1109/LED.2010.2045731
   Web of Science ®Google Scholar
• Sakurai, T. (2004). Perspectives of low-power VLSI’s. IEICE Transactions on Electronics, 87(4), 429–436.
   Google Scholar
• Saurabh, S., & Kumar, M. J. (2010). Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability. IEEE Transactions on Device and Materials Reliability, 10(3), 390–395. https://doi.org/10.1109/TDMR.2010.2054095
   Web of Science ®Google Scholar
• Seabaugh, A. C., & Zhang, Q. (2010). Low-voltage tunnel transistors for beyond CMOS logic. IEEE Procedings, 98(12), 2095–2110. https://doi.org/10.1109/JPROC.2010.2070470
   Web of Science ®Google Scholar
• Shalf, J. (2020). The future of computing beyond Moore‘s law. Philosophical Transactions of the Royal Society A, 378(2166), 20190061. https://doi.org/10.1098/rsta.2019.0061
   Google Scholar
• Singh, S., & Kondekar, P. N. (2017). A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: Process resilient design. Journal of Computational Electronics, 16(3), 685–695. https://doi.org/10.1007/s10825-017-0987-6
   Web of Science ®Google Scholar
• Singh, S., Sinha, R., & Kondekar, P. N. (2016). A novel ultra steep dynamically reconfigurable electrostatically doped silicon nanowire Schottky Barrier FET. Superlattices and Microstructures, 93, 40–49. https://doi.org/10.1016/j.spmi.2016.02.039
   Web of Science ®Google Scholar
• Theis, T. N., & Solomon, P. M. (2010). In quest of the next switch: Prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor. IEEE Procedings, 98(12), 2005–2014. https://doi.org/10.1109/JPROC.2010.2066531
   Web of Science ®Google Scholar
• Zhang, M., Knoch, J., Appenzeller, J., & Mantl, S. (2007). Improved carrier injection in ultrathin-body SOI Schottky-barrier MOSFETs. IEEE Electron Device Letter, 28(3), 223–225. https://doi.org/10.1109/LED.2007.891258
   Web of Science ®Google Scholar
• Zhang, M., Knoch, J., Zhao, Q. T., Lenk, S., Breuer, U., & Mantl, S. (2005). Schottky barrier height modulation using dopant segregation in Schottky-barrier SOI-MOSFETs. Proceedings of 35th European IEEE Solid-State Device Research Conference, 457–460. doi:10.1109/ESSDER.2005.1546683.
   Google Scholar