Study and evaluation of automatic offloading method in mixed offloading destination environment

References

• Alias, C., Darte, A., & Plesco, A. (2013, March). Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA. 2013 Design, Automation and Test in Europe (DATE), 575–23. https://doi.org/10.7873/date.2013.127
   Google Scholar
• Bertolli, C., Antao, S. F., Bercea, G. T., Jacob, A. C., Eichenberger, A. E., Chen, T., Sura, Z., Sung, H., Rokos, G., Appelhans, D., & O’Brien, K., “Integrating GPU support for OpenMP offloading directives into Clang,” ACM Second Workshop on the LLVM Compiler Infrastructure in HPC (LLVM’15), November. 2015.
   Google Scholar
• Chen, J., Joo, B., Watson, W., III, & Edwards, R., “Automatic offloading C++ expression templates to CUDA enabled GPUs,” 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, pp.2359–2368, May 2012.
   Google Scholar
• Deckard web site. 2021. http://github.com/skyhover/Deckard
   Google Scholar
• DPC++ web site 2021. https://www.intel.com/content/www/us/en/developer/tools/oneapi/dpc-library.html#gs.flx6xq
   Google Scholar
• Evans, P. C., & Annunziata, M., “Industrial internet: Pushing the boundaries,” Technical report of General Electric (GE) (General Electric), November. 2012.
   Google Scholar
• Gosling, J., Joy, B., & Steele, G. (2005). The Java language specification, third edition. Addison-Wesley. ISBN-10: 0-321-24678-0
   Google Scholar
• Hermann, M., Pentek, T., & Otto, B. (2016). Design principles for industrie 4.0 scenarios. 2016 49th Hawaii international conference on system sciences (HICSS), 3928–3937. https://doi.org/10.1109/hicss.2016.488
   Google Scholar
• Holland, J. H. (1992). Genetic algorithms. Scientific American, 267(1), 66–73. https://doi.org/10.1038/scientificamerican0792-66
   PubMed Web of Science ®Google Scholar
• Lee, S., Min, S. J., & Eigenmann, R., “OpenMP to GPGPU: A compiler framework for automatic translation and optimization,” 14th ACM SIGPLAN symposium on Principles and practice of parallel programming (PPoPP’09), 2009.
   Google Scholar
• Liu, C., Ho-Cheung, N., & Kwok-Hay So, H., “Automatic nested loop acceleration on FPGAs using soft CGRA overlay,” Second International Workshop on FPGAs for Software Programmers (FSP 2015), 2015.
   Google Scholar
• NAS.BT web site. 2022. https://www.nas.nasa.gov/publications/npb.html
   Google Scholar
• Polybench 3mm web site. 2012. https://web.cse.ohio-state.edu/pouchet.2/software/polybench/
   Google Scholar
• Polytope model web site. https://www.infosun.fim.uni-passau.de/cl/loopo/doc/loopo_doc/node3.html
   Google Scholar
• Putnam, A., Bennett, D., Dellinger, E., Mason, J., Sundararajan, P., & Eggers, S., “CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures,” IEEE 2008 International Conference on Field Programmable Logic and Applications, pp.173–178, September. 2008.
   Google Scholar
• Putnam, A., Caulfield, A. M., Chung, E. S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G. P., Gray, J., Haselman, M., Hauck, S., Heil, S., Hormati, A., Kim, J.-Y., Lanka, S., Larus, J., Peterson, E., Pope, S., … Burger, D., “A reconfigurable fabric for accelerating large-scale datacenter services,” Proceedings of the 41th Annual International Symposium on Computer Architecture (ISCA’14), pp.13–24, June 2014.
   Google Scholar
• ROSE compiler framework web site. 2022. http://rosecompiler.org/
   Google Scholar
• Sanders, J., & Kandrot, E. (2010). CUDA by example: An introduction to general-purpose GPU programming. Addison-Wesley. ISBN: 9780132180160
   Google Scholar
• Sefraoui, O., Aissaoui, M., & Eleuldj, M. (2012). OpenStack: Toward an open-source solution for cloud computing. International Journal of Computer Applications, 55(3), 38–42. https://doi.org/10.5120/8738-2991
   Google Scholar
• Shirahata, K., Sato, H., & Matsuoka, S., “Hybrid map task scheduling for GPU-based heterogeneous clusters,”IEEE Second International Conference on Cloud Computing Technology and Science (CloudCom), pp.733–740, December. 2010.
   Google Scholar
• Shitara, A., Nakahama, T., Yamada, M., Kamata, T., Nishikawa, Y., Yoshimi, M., & Amano, H., “Vegeta: An implementation and evaluation of development-support middleware on multiple OpenCL platform,” IEEE Second International Conference on Networking and Computing (ICNC 2011), pp.141–147, 2011.
   Google Scholar
• Sommer, L., Korinth, J., & Koch, A., “OpenMP device offloading to FPGA accelerators,” 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), pp.201–205, July 2017.
   Google Scholar
• Sterling, T., Anderson, M., & Brodowicz, M. (2018). High performance computing: Modern systems and practices. Morgan Kaufmann.
   Google Scholar
• Stone, J. E., Gohara, D., & Shi, G. (2010). OpenCL: A parallel programming standard for heterogeneous computing systems. Computing in Science & Engineering, 12(3), 66–73. https://doi.org/10.1109/MCSE.2010.69
   PubMed Web of Science ®Google Scholar
• Su, E., Tian, X., Girkar, M., Haab, G., Shah, S., & Petersen, P., “Compiler support of the workqueuing execution model for Intel SMP architectures,” In Fourth European Workshop on OpenMP, September. 2002.
   Google Scholar
• SYCL web site. 2020. https://www.khronos.org/sycl/
   Google Scholar
• Time domain finite impulse response filter Intel sample web site. https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/opencl/td-fir.html
   Google Scholar
• Time domain finite impulse response filter web site. 2020. http://www.omgwiki.org/hpec/files/hpec-challenge/tdfir.html
   Google Scholar
• Tomatsu, Y., Hiroyasu, T., Yoshimi, M., & Miki, M. (2010, August). gPot: Intelligent compiler for GPGPU using combinatorial optimization techniques. The 7th Joint Symposium between Doshisha University and Chonnam National University. Doshisha University and Chonnam National University.
   Google Scholar
• Wienke, S., Springer, P., Terboven, C., & an Mey, D. (2012). OpenACC-first experiences with real-world applications. Euro-Par 2012 Parallel Processing, 859–870. https://doi.org/10.1007/978-3-642-32820-6_85
   Google Scholar
• Wolfe, M., “Implementing the PGI accelerator model,” ACM the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, pp.43–50, March. 2010.
   Google Scholar
• Yamato, Y. (2015, October). Automatic system test technology of virtual machine software patch on IaaS cloud. IEEJ Transactions on Electrical and Electronic Engineering, 10(S1), 165–167. https://doi.org/10.1002/tee.22179
   Google Scholar
• Yamato, Y., Fukumoto, Y., & Kumazaki, H., “Analyzing machine noise for real time maintenance,” 2016 8th International Conference on Graphic and Image Processing (ICGIP 2016), October. 2016.
   Google Scholar
• Yamato, Y., “Proposal of optimum application deployment technology for heterogeneous IaaS cloud,” 2016 6th International Workshop on Computer Science and Engineering (WCSE 2016), pp.34–37, June 2016.
   Google Scholar
• Yamato, Y., Fukumoto, Y., & Kumazaki, H., “Security camera movie and ERP data matching system to prevent theft,” IEEE Consumer Communications and Networking Conference (CCNC 2017), pp.1021–1022, January. 2017.
   Google Scholar
• Yamato, Y., “Proposal of vital data analysis platform using wearable sensor,” 5th IIAE International Conference on Industrial Application Engineering 2017 (ICIAE2017), pp.138–143, March. 2017a.
   Google Scholar
• Yamato, Y., “Experiments of posture estimation on vehicles using wearable acceleration sensors,” The 3rd IEEE International Conference on Big Data Security on Cloud (BigDataSecurity 2017), pp.14–17, May 2017b.
   Google Scholar
• Yamato, Y. (2019). Study of parallel processing area extraction and data transfer number reduction for automatic GPU offloading of IoT applications. Journal of Intelligent Information Systems, Springer, 54(3), 567–584. https://doi.org/10.1007/s10844-019-00575-8
   Web of Science ®Google Scholar
• Yamato, Y., “Proposal of automatic offloading for function blocks of applications,” The 8th IIAE International Conference on Industrial Application Engineering 2020 (ICIAE 2020), pp.4–11, March. 2020.
   Google Scholar
• Yamato, Y. (2021). Automatic offloading method of loop statements of software to FPGA. International Journal of Parallel, Emergent and Distributed Systems, Taylor and Francis, 36(5), 482–494. https://doi.org/10.1080/17445760.2021.1916020
   Web of Science ®Google Scholar