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Materials and Manufacturing Processes Volume 18, 2003 - Issue 3
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Original Articles

Genetic Algorithms for High-Level Synthesis in VLSI Design

C. Mandal Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India; Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, WB 721302, IndiaCorrespondence[email protected]
&
P. P. Chakrabarti Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India
Pages 355-383 | Published online: 07 Feb 2007

References

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  • Mandal , C.A. , Chakrabarti , P.P. and Ghose , S. 1996 . Port assignment for dual and triple port memories using a genetic approach . Procs. of the Third Asia Pacific Conf. on Hardware Description Languages (APCHDL) 96 . 1996 . pp. 60 – 64 .
  • Mandal , C.A. , Chakrabarti , P.P. and Ghose , S. 1998 . A probabilistic estimator for the vertex deletion problem . Computers and Mathematics with Applications , 35 ( 6 ) : 1 – 4 .
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  • Mandal , C. and Zimmer , M. 1997 . High-level synthesis of structured data paths . IFIP TC10 WG 10.5 International Conference on Computer Hardware Description Languages and Their Applications . April 20–25 1997 . pp. 92 – 94 .
  • Tseng , C.J. and Siewiorek , D.P. 1986 . Automated synthesis of data paths in digital-systems . IEEE Trans. on C. A. D. , 5 : 379 – 395 .
  • Kung , S.Y. , Whitehouse , H.J. and Kailath , T. 1984 . VLSI and Modern Signal Processing Prentice Hall .
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  • Neil , J.P. and Denyer , P.B. 1992 . “ Simulated annealing based synthesis of fast discrete cosine transform blocks ” . In Algorithmic and Knowledge Based CAD for VLSI Edited by: Taylor , G. and Russel , G. 75 – 93 . Peter Peregrinus . Ch 4

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