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M. J. BELLIDO, A. J. ACOSTA, J. LUQUE, A. BARRIGA & M. VALENCIA. (1995) Evaluation of metastability transfer models: an application to an N-bistable CMOS synchronizer. International Journal of Electronics 79:5, pages 585-593.
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EBYG. FRIEDMAN. (1992) The limiting performance of a CMOS bistable register based on waveform considerations. International Journal of Electronics 73:2, pages 371-384.
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P. Ruiz de Clavijo Vazquez, J. Juan-Chico, M.J. Bellido, A. Acosta & M. Valencia. (2001) HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model. HALOTIS: High Accuracy Logic TIming simulator with inertial and degradation delay model.
J. Juan-Chico, P. Ruiz de Clavijo, M.J. Bellido, A.J. Acosta & M. Valenia. (2000) Inertial and degradation delay model for CMOS logic gates. Inertial and degradation delay model for CMOS logic gates.
M.J. Bellido-Díaz, J. Juan-Chico, A.J. Acosta, M. Valencia & J.L. Huertas. (2000) Logical modelling of delay degradation effect in static CMOS gates. IEE Proceedings - Circuits, Devices and Systems 147:2, pages 107.
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Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta & Manuel Valencia. 2000. Integrated Circuit Design. Integrated Circuit Design
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J. Juan-Chico, M.J. Bellido, A. Acosta, A. Barriga & M. Valencia. (1997) CMOS inverter maximum frequency of operation due to digital signal degradation. Electronics Letters 33:19, pages 1619.
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