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IETE Journal of Research Volume 61, 2015 - Issue 5
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Original Articles

Process-Induced Delay Variation in SWCNT, MWCNT, and Mixed CNT Interconnects

Manoj Kumar MajumderDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee247667, IndiaView further author information
,
Jainender KumarDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee247667, IndiaView further author information
&
Brajesh Kumar KaushikDepartment of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee247667, IndiaView further author information
Pages 533-540 | Published online: 16 Apr 2015

Citations (24)

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Read on this site (6)

Chopali Chanchal Sahu, Vijay Rao Kumbhare & Manoj Kumar Majumder. (2023) Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via. IETE Journal of Research 69:8, pages 5399-5411.
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V. Sulochana, C. Venkataiah, Sunil Agrawal & Balwinder Singh. (2023) Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic. IETE Journal of Research 69:3, pages 1328-1340.
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Gulafsha Bhatti, Takshashila Pathade, Yash Agrawal, Vinay Palaparthy, Bakul Gohel, Rutu Parekh & Mekala Girish Kumar. (2023) Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit. IETE Journal of Research 0:0, pages 1-16.
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Vijay Rao Kumbhare, Punya Prasanna Paltani & Manoj Kumar Majumder. (2022) Impact of Interconnect Spacing on Crosstalk for Multi-layered Graphene Nanoribbon. IETE Journal of Research 68:2, pages 1064-1073.
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A. Karthikeyan & P.S. Mallick. (2018) Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects. IETE Journal of Research 64:2, pages 296-305.
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Yash Agrawal, Rajeevan Chandel & Rohit Dhiman. (2017) Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System. IETE Journal of Research 63:2, pages 268-280.
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Articles from other publishers (18)

Vobulapuram Ramesh Kumar. (2023) Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks. ECS Journal of Solid State Science and Technology 12:5, pages 051007.
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Urmi Shah & Usha Mehta. 2023. Advances in VLSI and Embedded Systems. Advances in VLSI and Embedded Systems 187 201 .
Gurleen Dhillon & Karmjit Singh Sandha. (2021) Stability- and Crosstalk-Based Performance of Multi- and Double-walled Mixed CNT Bundles as Interconnect for Next-Generation Technology Nodes. Journal of Circuits, Systems and Computers 31:05.
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P. Uma Sathyakam, Shatarupa Bhattacharjee & Shubham Raj. (2021) Crosstalk Analysis of Triangular CNT Bundle Interconnects. Journal of Electronic Materials 50:12, pages 7017-7025.
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Baojun Liu, Cheng Li, Chuang Li & Shuang Zhang. (2021) Effect of temperature and single event transient on crosstalk in coupled single‐walled carbon nanotube (SWCNT) bundle interconnects. International Journal of Circuit Theory and Applications 49:10, pages 3408-3420.
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Shivangi Chandrakar, Deepika Gupta & Manoj Kumar Majumder. (2020) Role of Through Silicon Via in 3D Integration: Impact on Delay and Power. Journal of Circuits, Systems and Computers 30:03, pages 2150051.
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Gurleen Dhillon & Karmjit Singh Sandha. (2020) Mixed CNT bundles as VLSI interconnects for nanoscale technology nodes. Journal of Computational Electronics 20:1, pages 248-258.
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Takshashila Pathade, Yash Agrawal, Rutu Parekh & Mekala Girish Kumar. (2021) Structure Fortification of Mixed CNT Bundle Interconnects for Nano Integrated Circuits Using Constraint-Based Particle Swarm Optimization. IEEE Transactions on Nanotechnology 20, pages 194-204.
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Ch. Praveen Kumar, E. Sreenivasa Rao & P. Chandra Sekhar. (2020) A Novel Approach to Reduce the Crosstalk in Graphene Based Interconnects Using Ternary Logic. Journal of Computational and Theoretical Nanoscience 17:12, pages 5483-5494.
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Nikita Patel, Yash Agrawal, Rutu Parekh & Mekala Girish Kumar. (2020) Variability Analysis of On-chip Graphene Interconnects at Subthreshold Regime. Variability Analysis of On-chip Graphene Interconnects at Subthreshold Regime.
Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare & Manoj Kumar Majumder. (2019) Designing SRAM Using CMOS and CNTFET at 32 nm Technology. Designing SRAM Using CMOS and CNTFET at 32 nm Technology.
Nirmal DDrDr. (2019) DESIGN AND EFFICIENCY ANALYSIS OF NANOCARBON INTERCONNECT STRUCTURES. Journal of Electronics and Informatics 01:01, pages 12-23.
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Piratla Uma Sathyakam, Partha S. Mallick & Anmol Ajay Saxena. (2019) High‐speed sub‐threshold operation of carbon nanotube interconnects. IET Circuits, Devices & Systems 13:4, pages 526-533.
Crossref
P. Uma Sathyakam, Shaurya Das & A. Karthikeyan. (2019) Analysis of triangular CNT bundle interconnects for current mode signalling. Analysis of triangular CNT bundle interconnects for current mode signalling.
Balkrishna Choubey, Vijay Rao Kumbhare & Manoj Kumar Majumder. 2019. VLSI Design and Test. VLSI Design and Test 418 429 .
Vijay Rao Kumbhare, Punya Prasanna Paltani & Manoi Kumar Maiumder. (2018) Future of Graphene based Interconnecte Technology - A Reality or a Distant Dream. Future of Graphene based Interconnecte Technology - A Reality or a Distant Dream.
Songjie Zhao & Zhongliang Pan. (2018) Bandwidth expanding technology for dynamic crosstalk aware single-walled and multi-walled carbon nanotube bundle interconnects. Microelectronics Journal 78, pages 101-113.
Crossref
Karthikeyan & P.S. Mallick. (2016) Mixed CNT bundles as VLSI interconnects. Mixed CNT bundles as VLSI interconnects.

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